[OpenWrt-Devel] [RFC] ar71xx: Reset QCA955x SGMII link on speed change

[Sven Eckelmann]

On Friday 01 April 2016 14:41:47 Sven Eckelmann wrote:
[...]
>  static void qca955x_set_speed_xmii(int speed)
>  {
>  	void __iomem *base;
> @@ -381,6 +395,100 @@ static void qca955x_set_speed_xmii(int speed)
>  	base = ioremap_nocache(AR71XX_PLL_BASE, AR71XX_PLL_SIZE);
>  	__raw_writel(val, base + QCA955X_PLL_ETH_XMII_CONTROL_REG);
>  	iounmap(base);
> +
> +	// TODO: find out if something like qca955x_reset_xmii(); is needed
> +}

I was told that the GMAC0 also needs some special bits set to fix some
problems when switching between different half/full duplex speeds. The
only thing I was told is that qca955x_soc_gmac_set_link requires

    athr_reg_rmw_set(0xb900023c, 0x68000001);

Of course, it is not for QCAs current driver (which is a heavily
modified driver from OpenWrt) but their old one

    https://github.com/Existed/ethernet_driver/blob/3bde1bb60d31d78fee14cce0d8ea9539d8227a0d/qca955x.c#L587

I know that this register is IG_ACL_CSR for GMAC0 and BIT(0) is
IG_ACL_DISABLE and should only disable the ingress ACL. But I
have absolutely no idea what BIT(27), BIT(29) and BIT(30) are.

Does anyone know what these bits are? I personally don't have
yet feedback if this change really helps. But a equally bad
hack as the earlier one (sgmii) would be:


--- a/target/linux/ar71xx/files/arch/mips/ath79/dev-eth.c
+++ b/target/linux/ar71xx/files/arch/mips/ath79/dev-eth.c
@@ -387,6 +387,15 @@ static void ar934x_set_speed_ge0(int speed)
 #define QCA955X_GMAC_REG_SGMII_RESET_TX_CLK_N BIT(1)
 #define QCA955X_GMAC_REG_SGMII_RESET_RX_CLK_N BIT(0)
 
+#define QCA955X_GE0_BASE		0x19000000
+#define QCA955X_GE0_SIZE		0x2F0
+
+#define QCA955X_GE0_IG_ACL_CSR		0x23C
+#define QCA955X_GE0_IG_ACL_DISABLE	BIT(0)
+#define QCA955X_GE0_IG_ACL_MAGIC0	BIT(27)
+#define QCA955X_GE0_IG_ACL_MAGIC1	BIT(29)
+#define QCA955X_GE0_IG_ACL_MAGIC2	BIT(30)
+
 static void qca955x_set_speed_xmii(int speed)
 {
 	void __iomem *base;
@@ -396,7 +405,14 @@ static void qca955x_set_speed_xmii(int speed)
 	__raw_writel(val, base + QCA955X_PLL_ETH_XMII_CONTROL_REG);
 	iounmap(base);
 
-	// TODO: find out if something like qca955x_reset_xmii(); is needed
+	/* WARNING ugly PoC code ahead */
+	base = ioremap_nocache(QCA955X_GE0_BASE, QCA955X_GE0_SIZE);
+	val = QCA955X_GE0_IG_ACL_DISABLE |
+	      QCA955X_GE0_IG_ACL_MAGIC0 |
+	      QCA955X_GE0_IG_ACL_MAGIC1 |
+	      QCA955X_GE0_IG_ACL_MAGIC2;
+	__raw_writel(val, base + QCA955X_GE0_IG_ACL_CSR);
+	iounmap(base);
 }
 
 static void qca955x_reset_sgmii(void)
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