[OpenWrt-Devel] [PATCH 6/6] bcm53xx: R8000 handle PEX8603 switch

[Ian Kent]

On Wed, 2015-08-12 at 22:01 +0200, Hauke Mehrtens wrote:
> On 07/15/2015 12:11 PM, Ian Kent wrote:
> > On Tue, 2015-07-14 at 18:19 +0200, Rafał Miłecki wrote:
> >> On 28 June 2015 at 05:37, Ian Kent <raven at themaw.net> wrote:
> >>> Let me rework this using the bus number as you recommend.
> >>> I'll repost my updated patch series once I've done that.
> >>
> >> Hi Ian,
> >>
> >> Is there any chance you'll find a moment for it anytime soon? It'd be
> >> awesome to get R8000 support for CC release.
> > 
> > I have reworked the patch and a broken package build problem I had is
> > gone but I didn't get time to fix build problems with a third patch I
> > have.
> > 
> > Just didn't get time last weekend and this week has been quite busy too.
> > I'll try and get onto this in the next few days.
> > 
> > Ian
> 
> Hi Ian,
> 
> you patch looks better than the hack Broadcom did in their vendor driver.

I thought so, ;)

> 
> Could you send me a lspci output or the content of /proc/bus/pci/devices
> of the original firmware or of OpenWrt with your patch applied? I would
> prefer lspci because it is easier to read but cat from
> /proc/bus/pci/devices also works. I do not have such a device and want
> to understand how this PCIe switch looks like on the software side, so
> we can fix the domain, bus, slot, function mixup.

I haven't been able to build OpenWrt for a while now and that's why I
haven't been able to test my changes to the patch.

I really wish we could avoid committing changes that don't build but I
know it isn't that simple.

I have got some other lists (around somewhere) based on output, mostly
from the Vendor firmware, and one where I went through the devices and
listed what they are along with and their pci ids so I could try and
understand what was going on.

I could try and find that and post it if it would be useful.
Note that it was just used to understand what was what so it isn't
pretty but should have quite a bit of info in it.

There's no question the current patch is wrong so I don't recommend it
be used.

I can however post my updated patch now on the understanding that it
hasn't been tested at all, which might be good for initial review
anyway.

> 
> On the hardware side this SoC has 3 PCIe controllers, but one shares a
> PHY with the USB 3.0 controller. Instead of using the 3rd PCIe
> controller they used USB 3.0 and split one of the PCIe controllers into
> 2 PCIE lanes.

Right, I didn't get that, mmm ...

Ian
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