[PATCH 3/3] realtek: add support for Panasonic Switch-M8eG PN28080K
INAGAKI Hiroshi
musashino.open at gmail.com
Sat Oct 2 23:53:49 PDT 2021
Panasonic M8eG PN28080K is a 8 + 1 port gigabit switch, based on
RTL8380M.
Specification:
- SoC : Realtek RTL8380M
- RAM : DDR3 128 MiB (Winbond W631GG8KB-15)
- Flash : SPI-NOR 32 MiB (Macronix MX25L25635FMI-10G)
- Ethernet : 10/100/1000 Mbps x8 + 1
- port 1-8 : TP, RTL8218B (SoC)
- port 9 : SFP, RTL8380M (SoC)
- LEDs/Keys : 7x / 1x
- UART : RS-232 port on the front panel (connector: RJ-45)
- 3:TX, 4:GND, 5:GND, 6:RX (pin number: RJ-45)
- 9600n8
- Power : 100-240 VAC, 50/60 Hz, 0.5 A
- Plug : IEC 60320-C13
- Stock OS : VxWorks based
Flash instruction using initramfs image:
1. Prepare the TFTP server with the IP address 192.168.1.111
2. Rename the OpenWrt initramfs image to "0101A8C0.img" and place it to
the TFTP directory
3. Download the official upgrading firmware (ex: pn28080k_v30000.rom)
and place it to the TFTP directory
4. Boot M8eG and interrupt the U-Boot with Ctrl + C keys
5. Execute the following commands and boot with the OpenWrt initramfs
image
rtk network on
tftpboot 0x81000000
bootm
6. Backup mtdblock files to the computer by scp or anything and reboot
7. Interrupt the U-Boot and execute the following commands to re-create
filesystem in the flash
ffsmount c:/
ffsfmt c:/
this step takes a long time, about ~ 4 mins
8. Execute the following commands to put the official images to the
filesystem
updatert <official image>
example:
updatert pn28080k_v30000.rom
this step takes about ~ 40 secs
9. Set the environment variables of the U-Boot by the following commands
setenv loadaddr 0xb4e00000
setenv bootcmd bootm
saveenv
10: Download the OpenWrt initramfs image and boot with it
tftpboot 0x81000000 0101A8C0.img
bootm
11: On the initramfs image, download the sysupgrade image and perform
sysupgrade with it
sysupgrade <imagename>
12: Wait ~ 120 seconds to complete flashing
Note:
- "Switch-M8eG" is a model name, and "PN28080K" is a model number.
Switch-M8eG has an another (old) model number ("PN28080"), it's not a
Realtek based hardware.
- Switch-M8eG has a "POWER" LED (Green), but it's not connected to any
GPIO pin.
- The U-Boot checks the runtime images in the flash when booting and
fails to execute anything in "bootcmd" variable if the images are not
exsisting.
- A filesystem is formed in the flash (0x100000-0x1DFFFFF) on the stock
firmware and it includes the stock images, configuration files and
checksum files. It's unknown format, can't be managed on the OpenWrt.
To get the enough space for OpenWrt, move the filesystem to the head
of "fs_reserved" partition by execution of "ffsfmt" and "updatert".
Back to the stock firmware:
1. Delete "loadaddr" variable and set "bootcmd" to the original value
on U-Boot:
setenv loadaddr
setenv bootcmd 'bootm 0x81000000'
on OpenWrt:
fw_setenv loadaddr
fw_setenv bootcmd 'bootm 0x81000000'
2. Perform reset or reboot
on U-Boot:
reset
on OpenWrt:
reboot
Signed-off-by: INAGAKI Hiroshi <musashino.open at gmail.com>
---
.../rtl8380_panasonic_m8eg-pn28080k.dts | 103 ++++++++
.../rtl83xx_panasonic_mxxeg-pn28xx0k.dtsi | 216 +++++++++++++++++
.../rtl8380_panasonic_m8eg-pn28080k.dts | 107 +++++++++
.../rtl83xx_panasonic_mxxeg-pn28xx0k.dtsi | 220 ++++++++++++++++++
target/linux/realtek/image/Makefile | 10 +
5 files changed, 656 insertions(+)
create mode 100644 target/linux/realtek/dts-5.10/rtl8380_panasonic_m8eg-pn28080k.dts
create mode 100644 target/linux/realtek/dts-5.10/rtl83xx_panasonic_mxxeg-pn28xx0k.dtsi
create mode 100644 target/linux/realtek/dts-5.4/rtl8380_panasonic_m8eg-pn28080k.dts
create mode 100644 target/linux/realtek/dts-5.4/rtl83xx_panasonic_mxxeg-pn28xx0k.dtsi
diff --git a/target/linux/realtek/dts-5.10/rtl8380_panasonic_m8eg-pn28080k.dts b/target/linux/realtek/dts-5.10/rtl8380_panasonic_m8eg-pn28080k.dts
new file mode 100644
index 0000000000..df470c377e
--- /dev/null
+++ b/target/linux/realtek/dts-5.10/rtl8380_panasonic_m8eg-pn28080k.dts
@@ -0,0 +1,103 @@
+// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
+
+#include "rtl838x.dtsi"
+#include "rtl83xx_panasonic_mxxeg-pn28xx0k.dtsi"
+
+/ {
+ compatible = "panasonic,m8eg-pn28080k", "realtek,rtl838x-soc";
+ model = "Panasonic Switch-M8eG PN28080K";
+
+ aliases {
+ led-boot = &led_status_eco_green;
+ led-failsafe = &led_status_eco_amber;
+ led-running = &led_status_eco_green;
+ led-upgrade = &led_status_eco_green;
+ };
+
+ sfp0: sfp-p9 {
+ compatible = "sff,sfp";
+ i2c-bus = <&i2c0>;
+ tx-fault-gpio = <&gpio1 0 GPIO_ACTIVE_HIGH>;
+ tx-disable-gpio = <&gpio1 1 GPIO_ACTIVE_HIGH>;
+ mod-def0-gpio = <&gpio1 2 GPIO_ACTIVE_LOW>;
+ los-gpio = <&gpio1 3 GPIO_ACTIVE_HIGH>;
+ };
+};
+
+&leds {
+ led_status_eco_amber: status_eco_amber {
+ label = "amber:status_eco";
+ gpios = <&gpio2 1 GPIO_ACTIVE_LOW>;
+ };
+
+ led_status_eco_green: status_eco_green {
+ label = "green:status_eco";
+ gpios = <&gpio2 2 GPIO_ACTIVE_LOW>;
+ };
+};
+
+&i2c_gpio_0 {
+ scl-gpios = <&gpio0 0 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
+ sda-gpios = <&gpio0 1 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
+};
+
+&i2c_gpio_1 {
+ scl-gpios = <&gpio0 12 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
+ sda-gpios = <&gpio0 13 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
+};
+
+ðernet0 {
+ mdio-bus {
+ compatible = "realtek,rtl838x-mdio";
+ regmap = <ðernet0>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ INTERNAL_PHY(8)
+ INTERNAL_PHY(9)
+ INTERNAL_PHY(10)
+ INTERNAL_PHY(11)
+ INTERNAL_PHY(12)
+ INTERNAL_PHY(13)
+ INTERNAL_PHY(14)
+ INTERNAL_PHY(15)
+
+ INTERNAL_PHY(24)
+ };
+};
+
+&switch0 {
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ SWITCH_PORT(8, 1, internal)
+ SWITCH_PORT(9, 2, internal)
+ SWITCH_PORT(10, 3, internal)
+ SWITCH_PORT(11, 4, internal)
+ SWITCH_PORT(12, 5, internal)
+ SWITCH_PORT(13, 6, internal)
+ SWITCH_PORT(14, 7, internal)
+ SWITCH_PORT(15, 8, internal)
+
+ port at 24 {
+ reg = <24>;
+ label = "lan9";
+ phy-mode = "1000base-x";
+ phy-handle = <&phy24>;
+ managed = "in-band-status";
+ sfp = <&sfp0>;
+ };
+
+ port at 28 {
+ ethernet = <ðernet0>;
+ reg = <28>;
+ phy-mode = "internal";
+
+ fixed-link {
+ speed = <1000>;
+ full-duplex;
+ };
+ };
+ };
+};
diff --git a/target/linux/realtek/dts-5.10/rtl83xx_panasonic_mxxeg-pn28xx0k.dtsi b/target/linux/realtek/dts-5.10/rtl83xx_panasonic_mxxeg-pn28xx0k.dtsi
new file mode 100644
index 0000000000..d41213f1fd
--- /dev/null
+++ b/target/linux/realtek/dts-5.10/rtl83xx_panasonic_mxxeg-pn28xx0k.dtsi
@@ -0,0 +1,216 @@
+// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
+
+#include <dt-bindings/input/input.h>
+#include <dt-bindings/gpio/gpio.h>
+
+/ {
+ chosen {
+ bootargs = "console=ttyS0,9600";
+ };
+
+ memory at 0 {
+ device_type = "memory";
+ reg = <0x0 0x8000000>;
+ };
+
+ leds: leds {
+ compatible = "gpio-leds";
+
+ any_collision {
+ label = "amber:any_col";
+ gpios = <&gpio2 0 GPIO_ACTIVE_LOW>;
+ };
+
+ giga {
+ label = "green:giga";
+ gpios = <&gpio2 8 GPIO_ACTIVE_LOW>;
+ };
+
+ 100m {
+ label = "green:100m";
+ gpios = <&gpio2 9 GPIO_ACTIVE_LOW>;
+ };
+
+ full_duplex {
+ label = "green:full";
+ gpios = <&gpio2 10 GPIO_ACTIVE_LOW>;
+ };
+
+ loop_history {
+ label = "green:loop_history";
+ gpios = <&gpio2 11 GPIO_ACTIVE_LOW>;
+ };
+ };
+
+ keys {
+ compatible = "gpio-keys-polled";
+ poll-interval = <20>;
+
+ led_mode {
+ label = "led-mode";
+ gpios = <&gpio2 15 GPIO_ACTIVE_LOW>;
+ linux,code = <BTN_0>;
+ };
+ };
+
+ gpio-restart {
+ compatible = "gpio-restart";
+ gpios = <&gpio2 3 GPIO_ACTIVE_HIGH>;
+ active-delay = <100>;
+ inactive-delay = <100>;
+ wait-delay = <3000>;
+ };
+
+ /* Switch-M*eG PN28xx0K has no RTL8231 chip */
+ /delete-node/ rtl8231-gpio;
+
+ i2c_gpio_0: i2c-gpio-0 {
+ compatible = "i2c-gpio";
+ i2c-gpio,delay-us = <2>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ gpio1: gpio at 20 {
+ compatible = "nxp,pca9555";
+ reg = <0x20>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ };
+
+ gpio2: gpio at 75 {
+ compatible = "nxp,pca9539";
+ reg = <0x75>;
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ /*
+ * GPIO14 (IO1_6): Shift Register RESET (port LED)
+ * - Switch-M8eG PN28080K: 3x 74HC164
+ * - Switch-M24eG PN28240K: 6x 74HC164
+ * - Switch-M48eG PN28480K: 12x 74HC164
+ */
+ portled_sregister_reset {
+ gpio-hog;
+ gpios = <14 GPIO_ACTIVE_HIGH>;
+ output-high;
+ line-name = "portled-sregister-reset";
+ };
+ };
+ };
+
+ i2c_gpio_1: i2c-gpio-1 {
+ compatible = "i2c-gpio";
+ i2c-gpio,delay-us = <2>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ i2c-switch at 70 {
+ compatible = "nxp,pca9545";
+ reset-gpios = <&gpio2 13 GPIO_ACTIVE_LOW>;
+ reg = <0x70>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ /*
+ * - Switch-M8eG PN28080K: 0 (sfp p9)
+ * - Switch-M24eG PN28240K: 0-1 (sfp p23-p24)
+ * - Switch-M48eG PN28480K: 0-3 (sfp p45-p48)
+ */
+ i2c0: i2c at 0 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0>;
+ };
+
+ i2c1: i2c at 1 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <1>;
+ };
+
+ i2c2: i2c at 2 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <2>;
+ };
+
+ i2c3: i2c at 3 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <3>;
+ };
+ };
+ };
+};
+
+&spi0 {
+ status = "okay";
+
+ flash at 0 {
+ compatible = "jedec,spi-nor";
+ reg = <0>;
+ spi-max-frequency = <10000000>;
+
+ partitions {
+ compatible = "fixed-partitions";
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ partition at 0 {
+ label = "u-boot";
+ reg = <0x0 0x80000>;
+ read-only;
+ };
+
+ partition at 80000 {
+ label = "u-boot-env";
+ reg = <0x80000 0x10000>;
+ };
+
+ partition at 90000 {
+ label = "u-boot-env2";
+ reg = <0x90000 0x10000>;
+ };
+
+ partition at a0000 {
+ label = "sysinfo";
+ reg = <0xa0000 0x60000>;
+ read-only;
+ };
+
+ /*
+ * 0x100000 - 0x1DFFFFF
+ * Filesystem area for runtime images and
+ * configuration files in stock firmware
+ */
+
+ /*
+ * re-created filesystem area, 2x stock images
+ * are included with checksum files
+ */
+ partition at 100000 {
+ label = "fs_reserved";
+ reg = <0x100000 0xd00000>;
+ };
+
+ /* free area for OpenWrt */
+ partition at e00000 {
+ compatible = "denx,uimage";
+ label = "firmware";
+ reg = <0xe00000 0x1000000>;
+ };
+
+ partition at 1e00000 {
+ label = "vlog_data";
+ reg = <0x1e00000 0x100000>;
+ read-only;
+ };
+
+ partition at 1f00000 {
+ label = "elog_data";
+ reg = <0x1f00000 0x100000>;
+ read-only;
+ };
+ };
+ };
+};
diff --git a/target/linux/realtek/dts-5.4/rtl8380_panasonic_m8eg-pn28080k.dts b/target/linux/realtek/dts-5.4/rtl8380_panasonic_m8eg-pn28080k.dts
new file mode 100644
index 0000000000..d369e52625
--- /dev/null
+++ b/target/linux/realtek/dts-5.4/rtl8380_panasonic_m8eg-pn28080k.dts
@@ -0,0 +1,107 @@
+// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
+
+#include "rtl838x.dtsi"
+#include "rtl83xx_panasonic_mxxeg-pn28xx0k.dtsi"
+
+/ {
+ compatible = "panasonic,m8eg-pn28080k", "realtek,rtl838x-soc";
+ model = "Panasonic Switch-M8eG PN28080K";
+
+ aliases {
+ led-boot = &led_status_eco_green;
+ led-failsafe = &led_status_eco_amber;
+ led-running = &led_status_eco_green;
+ led-upgrade = &led_status_eco_green;
+ };
+
+ sfp0: sfp-p9 {
+ compatible = "sff,sfp";
+ i2c-bus = <&i2c0>;
+ tx-fault-gpio = <&gpio1 0 GPIO_ACTIVE_HIGH>;
+ tx-disable-gpio = <&gpio1 1 GPIO_ACTIVE_HIGH>;
+ mod-def0-gpio = <&gpio1 2 GPIO_ACTIVE_LOW>;
+ los-gpio = <&gpio1 3 GPIO_ACTIVE_HIGH>;
+ };
+};
+
+&leds {
+ led_status_eco_amber: status_eco_amber {
+ label = "amber:status_eco";
+ gpios = <&gpio2 1 GPIO_ACTIVE_LOW>;
+ };
+
+ led_status_eco_green: status_eco_green {
+ label = "green:status_eco";
+ gpios = <&gpio2 2 GPIO_ACTIVE_LOW>;
+ };
+};
+
+&i2c_gpio_0 {
+ /* SoC GPIO 0 */
+ scl-gpios = <&gpio0 24 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
+ /* SoC GPIO 1 */
+ sda-gpios = <&gpio0 25 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
+};
+
+&i2c_gpio_1 {
+ /* SoC GPIO 12 */
+ scl-gpios = <&gpio0 20 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
+ /* SoC GPIO 13 */
+ sda-gpios = <&gpio0 21 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
+};
+
+ðernet0 {
+ mdio-bus {
+ compatible = "realtek,rtl838x-mdio";
+ regmap = <ðernet0>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ INTERNAL_PHY(8)
+ INTERNAL_PHY(9)
+ INTERNAL_PHY(10)
+ INTERNAL_PHY(11)
+ INTERNAL_PHY(12)
+ INTERNAL_PHY(13)
+ INTERNAL_PHY(14)
+ INTERNAL_PHY(15)
+
+ INTERNAL_PHY(24)
+ };
+};
+
+&switch0 {
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ SWITCH_PORT(8, 1, internal)
+ SWITCH_PORT(9, 2, internal)
+ SWITCH_PORT(10, 3, internal)
+ SWITCH_PORT(11, 4, internal)
+ SWITCH_PORT(12, 5, internal)
+ SWITCH_PORT(13, 6, internal)
+ SWITCH_PORT(14, 7, internal)
+ SWITCH_PORT(15, 8, internal)
+
+ port at 24 {
+ reg = <24>;
+ label = "lan9";
+ phy-mode = "1000base-x";
+ phy-handle = <&phy24>;
+ managed = "in-band-status";
+ sfp = <&sfp0>;
+ };
+
+ port at 28 {
+ ethernet = <ðernet0>;
+ reg = <28>;
+ phy-mode = "internal";
+
+ fixed-link {
+ speed = <1000>;
+ full-duplex;
+ };
+ };
+ };
+};
diff --git a/target/linux/realtek/dts-5.4/rtl83xx_panasonic_mxxeg-pn28xx0k.dtsi b/target/linux/realtek/dts-5.4/rtl83xx_panasonic_mxxeg-pn28xx0k.dtsi
new file mode 100644
index 0000000000..3075cbe9c8
--- /dev/null
+++ b/target/linux/realtek/dts-5.4/rtl83xx_panasonic_mxxeg-pn28xx0k.dtsi
@@ -0,0 +1,220 @@
+// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
+
+#include <dt-bindings/input/input.h>
+#include <dt-bindings/gpio/gpio.h>
+
+/ {
+ chosen {
+ bootargs = "console=ttyS0,9600";
+ };
+
+ memory at 0 {
+ device_type = "memory";
+ reg = <0x0 0x8000000>;
+ };
+
+ leds: leds {
+ compatible = "gpio-leds";
+
+ any_collision {
+ label = "amber:any_col";
+ gpios = <&gpio2 0 GPIO_ACTIVE_LOW>;
+ };
+
+ giga {
+ label = "green:giga";
+ gpios = <&gpio2 8 GPIO_ACTIVE_LOW>;
+ };
+
+ 100m {
+ label = "green:100m";
+ gpios = <&gpio2 9 GPIO_ACTIVE_LOW>;
+ };
+
+ full_duplex {
+ label = "green:full";
+ gpios = <&gpio2 10 GPIO_ACTIVE_LOW>;
+ };
+
+ loop_history {
+ label = "green:loop_history";
+ gpios = <&gpio2 11 GPIO_ACTIVE_LOW>;
+ };
+ };
+
+ keys {
+ compatible = "gpio-keys-polled";
+ poll-interval = <20>;
+
+ led_mode {
+ label = "led-mode";
+ gpios = <&gpio2 15 GPIO_ACTIVE_LOW>;
+ linux,code = <BTN_0>;
+ };
+ };
+
+ gpio-restart {
+ compatible = "gpio-restart";
+ gpios = <&gpio2 3 GPIO_ACTIVE_HIGH>;
+ active-delay = <100>;
+ inactive-delay = <100>;
+ wait-delay = <3000>;
+ };
+
+ /* Switch-M*eG PN28xx0K has no RTL8231 chip */
+ /delete-node/ rtl8231-gpio;
+
+ i2c_gpio_0: i2c-gpio-0 {
+ compatible = "i2c-gpio";
+ i2c-gpio,delay-us = <2>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ gpio1: gpio at 20 {
+ compatible = "nxp,pca9555";
+ reg = <0x20>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ };
+
+ gpio2: gpio at 75 {
+ compatible = "nxp,pca9539";
+ reg = <0x75>;
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ /*
+ * GPIO14 (IO1_6): Shift Register RESET (port LED)
+ * - Switch-M8eG PN28080K: 3x 74HC164
+ * - Switch-M24eG PN28240K: 6x 74HC164
+ * - Switch-M48eG PN28480K: 12x 74HC164
+ */
+ portled_sregister_reset {
+ gpio-hog;
+ gpios = <14 GPIO_ACTIVE_HIGH>;
+ output-high;
+ line-name = "portled-sregister-reset";
+ };
+ };
+ };
+
+ i2c_gpio_1: i2c-gpio-1 {
+ compatible = "i2c-gpio";
+ i2c-gpio,delay-us = <2>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ i2c-switch at 70 {
+ compatible = "nxp,pca9545";
+ reset-gpios = <&gpio2 13 GPIO_ACTIVE_LOW>;
+ reg = <0x70>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ /*
+ * - Switch-M8eG PN28080K: 0 (sfp p9)
+ * - Switch-M24eG PN28240K: 0-1 (sfp p23-p24)
+ * - Switch-M48eG PN28480K: 0-3 (sfp p45-p48)
+ */
+ i2c0: i2c at 0 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0>;
+ };
+
+ i2c1: i2c at 1 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <1>;
+ };
+
+ i2c2: i2c at 2 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <2>;
+ };
+
+ i2c3: i2c at 3 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <3>;
+ };
+ };
+ };
+};
+
+&gpio0 {
+ indirect-access-bus-id = <0>;
+};
+
+&spi0 {
+ status = "okay";
+
+ flash at 0 {
+ compatible = "jedec,spi-nor";
+ reg = <0>;
+ spi-max-frequency = <10000000>;
+
+ partitions {
+ compatible = "fixed-partitions";
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ partition at 0 {
+ label = "u-boot";
+ reg = <0x0 0x80000>;
+ read-only;
+ };
+
+ partition at 80000 {
+ label = "u-boot-env";
+ reg = <0x80000 0x10000>;
+ };
+
+ partition at 90000 {
+ label = "u-boot-env2";
+ reg = <0x90000 0x10000>;
+ };
+
+ partition at a0000 {
+ label = "sysinfo";
+ reg = <0xa0000 0x60000>;
+ read-only;
+ };
+
+ /*
+ * 0x100000 - 0x1DFFFFF
+ * Filesystem area for runtime images and
+ * configuration files in stock firmware
+ */
+
+ /*
+ * re-created filesystem area, 2x stock images
+ * are included with checksum files
+ */
+ partition at 100000 {
+ label = "fs_reserved";
+ reg = <0x100000 0xd00000>;
+ };
+
+ /* free area for OpenWrt */
+ partition at e00000 {
+ compatible = "denx,uimage";
+ label = "firmware";
+ reg = <0xe00000 0x1000000>;
+ };
+
+ partition at 1e00000 {
+ label = "vlog_data";
+ reg = <0x1e00000 0x100000>;
+ read-only;
+ };
+
+ partition at 1f00000 {
+ label = "elog_data";
+ reg = <0x1f00000 0x100000>;
+ read-only;
+ };
+ };
+ };
+};
diff --git a/target/linux/realtek/image/Makefile b/target/linux/realtek/image/Makefile
index 5e4b4cde80..ed1e9e5212 100644
--- a/target/linux/realtek/image/Makefile
+++ b/target/linux/realtek/image/Makefile
@@ -112,6 +112,16 @@ define Device/netgear_gs310tp-v1
endef
TARGET_DEVICES += netgear_gs310tp-v1
+define Device/panasonic_m8eg-pn28080k
+ SOC := rtl8380
+ IMAGE_SIZE := 16384k
+ DEVICE_VENDOR := Panasonic
+ DEVICE_MODEL := Switch-M8eG
+ DEVICE_VARIANT := PN28080K
+ DEVICE_PACKAGES := kmod-i2c-mux-pca954x
+endef
+TARGET_DEVICES += panasonic_m8eg-pn28080k
+
define Device/zyxel_gs1900
SOC := rtl8380
IMAGE_SIZE := 6976k
--
2.33.0.windows.2
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