[PATCH] cn913x: add support for iEi Puzzle-M901/Puzzle-M902
eveans2002 at gmail.com
eveans2002 at gmail.com
Sun Jun 6 14:56:23 PDT 2021
From: Ian Chang <ianchang at ieiworld.com>
Hardware specification
----------------------
* CN9130 SoC, Quad-core ARMv8 Cortex-72 @ 2200 MHz
* 4 GB DDR
* 4 GB eMMC
mmcblk0
├─mmcblk0p1 64M kernel_1
├─mmcblk0p2 64M kernel_2
├─mmcblk0p3 512M rootfs_1
├─mmcblk0p4 512M rootfs_2
├─mmcblk0p5 512M Reserved
├─mmcblk0p6 64M Reserved
└─mmcblk0p7 1.8G rootfs_data
* 4 MB (SPI Flash)
* 6 x 2.5 Gigabit ports (Puzzle-M901)
- External PHY with 6 ports (AQR112R)
* 6 x 2.5 Gigabit ports (Puzzle-M902)
- External PHY with 6 ports (AQR112R)
3 x 10 Gigabit ports (Puzzle-M902)
- External PHY with 3 ports (AQR113R)
* 4 x Front panel LED
* 1 x USB 3.0
* Reset button on Rear panel
* UART (115200 8N1,header on PCB)
Signed-off-by: Ian Chang <ianchang at ieiworld.com>
---
.../base-files/etc/board.d/02_network | 6 +
target/linux/mvebu/cortexa72/config-5.4 | 5 +
.../dts/marvell/puzzle-armada-common.dtsi | 11 +
.../boot/dts/marvell/puzzle-armada-cp110.dtsi | 12 +
.../arm64/boot/dts/marvell/puzzle-cn9130.dtsi | 37 +++
.../dts/marvell/puzzle-m901-cn9130-db.dts | 241 ++++++++++++++++
.../dts/marvell/puzzle-m901-cn9131-db.dts | 182 ++++++++++++
.../dts/marvell/puzzle-m902-cn9130-db.dts | 261 ++++++++++++++++++
.../dts/marvell/puzzle-m902-cn9131-db.dts | 170 ++++++++++++
.../dts/marvell/puzzle-m902-cn9132-db.dts | 209 ++++++++++++++
target/linux/mvebu/image/cortexa72.mk | 24 ++
11 files changed, 1158 insertions(+)
create mode 100644 target/linux/mvebu/files/arch/arm64/boot/dts/marvell/puzzle-armada-common.dtsi
create mode 100644 target/linux/mvebu/files/arch/arm64/boot/dts/marvell/puzzle-armada-cp110.dtsi
create mode 100644 target/linux/mvebu/files/arch/arm64/boot/dts/marvell/puzzle-cn9130.dtsi
create mode 100644 target/linux/mvebu/files/arch/arm64/boot/dts/marvell/puzzle-m901-cn9130-db.dts
create mode 100644 target/linux/mvebu/files/arch/arm64/boot/dts/marvell/puzzle-m901-cn9131-db.dts
create mode 100644 target/linux/mvebu/files/arch/arm64/boot/dts/marvell/puzzle-m902-cn9130-db.dts
create mode 100644 target/linux/mvebu/files/arch/arm64/boot/dts/marvell/puzzle-m902-cn9131-db.dts
create mode 100644 target/linux/mvebu/files/arch/arm64/boot/dts/marvell/puzzle-m902-cn9132-db.dts
diff --git a/target/linux/mvebu/cortexa72/base-files/etc/board.d/02_network b/target/linux/mvebu/cortexa72/base-files/etc/board.d/02_network
index 9ab3c8174d..0be4191b69 100755
--- a/target/linux/mvebu/cortexa72/base-files/etc/board.d/02_network
+++ b/target/linux/mvebu/cortexa72/base-files/etc/board.d/02_network
@@ -21,6 +21,12 @@ marvell,armada8040-db)
marvell,armada7040-db)
ucidef_set_interfaces_lan_wan "eth0 eth2" "eth1"
;;
+marvell,cn9131)
+ ucidef_set_interfaces_lan_wan "eth1 eth2 eth3 eth4 eth5" "eth0"
+ ;;
+marvell,cn9132)
+ ucidef_set_interfaces_lan_wan "eth1 eth2 eth3 eth4 eth5 eth10 eth11 eth12" "eth0"
+ ;;
*)
ucidef_set_interface_lan "eth0"
;;
diff --git a/target/linux/mvebu/cortexa72/config-5.4 b/target/linux/mvebu/cortexa72/config-5.4
index 5727ae5918..00ab25f91d 100644
--- a/target/linux/mvebu/cortexa72/config-5.4
+++ b/target/linux/mvebu/cortexa72/config-5.4
@@ -175,3 +175,8 @@ CONFIG_THREAD_INFO_IN_TASK=y
CONFIG_UNMAP_KERNEL_AT_EL0=y
CONFIG_VMAP_STACK=y
CONFIG_ZONE_DMA32=y
+# CONFIG_PUZZLE-M90x
+CONFIG_RTC_DRV_DS1307=y
+# CONFIG_RTC_DRV_MV is not set
+# CONFIG_RTC_DRV_ARMADA38X is not set
+
diff --git a/target/linux/mvebu/files/arch/arm64/boot/dts/marvell/puzzle-armada-common.dtsi b/target/linux/mvebu/files/arch/arm64/boot/dts/marvell/puzzle-armada-common.dtsi
new file mode 100644
index 0000000000..c04c6c4750
--- /dev/null
+++ b/target/linux/mvebu/files/arch/arm64/boot/dts/marvell/puzzle-armada-common.dtsi
@@ -0,0 +1,11 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (C) 2016 Marvell Technology Group Ltd.
+ */
+
+/* Common definitions used by Armada 7K/8K DTs */
+#define PASTER(x, y) x ## y
+#define EVALUATOR(x, y) PASTER(x, y)
+#define CP11X_LABEL(name) EVALUATOR(CP11X_NAME, EVALUATOR(_, name))
+#define CP11X_NODE_NAME(name) EVALUATOR(CP11X_NAME, EVALUATOR(-, name))
+#define ADDRESSIFY(addr) EVALUATOR(0x, addr)
diff --git a/target/linux/mvebu/files/arch/arm64/boot/dts/marvell/puzzle-armada-cp110.dtsi b/target/linux/mvebu/files/arch/arm64/boot/dts/marvell/puzzle-armada-cp110.dtsi
new file mode 100644
index 0000000000..4fd33b0fa5
--- /dev/null
+++ b/target/linux/mvebu/files/arch/arm64/boot/dts/marvell/puzzle-armada-cp110.dtsi
@@ -0,0 +1,12 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (C) 2019 Marvell Technology Group Ltd.
+ *
+ * Device Tree file for Marvell Armada CP110.
+ */
+
+#define CP11X_TYPE cp110
+
+#include "armada-cp11x.dtsi"
+
+#undef CP11X_TYPE
diff --git a/target/linux/mvebu/files/arch/arm64/boot/dts/marvell/puzzle-cn9130.dtsi b/target/linux/mvebu/files/arch/arm64/boot/dts/marvell/puzzle-cn9130.dtsi
new file mode 100644
index 0000000000..a2b7e5ec97
--- /dev/null
+++ b/target/linux/mvebu/files/arch/arm64/boot/dts/marvell/puzzle-cn9130.dtsi
@@ -0,0 +1,37 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (C) 2019 Marvell International Ltd.
+ *
+ * Device tree for the CN9130 SoC.
+ */
+
+#include "armada-ap807-quad.dtsi"
+
+/ {
+ model = "Marvell Armada CN9130 SoC";
+ compatible = "marvell,cn9130", "marvell,armada-ap807-quad",
+ "marvell,armada-ap807";
+};
+
+/*
+ * Instantiate the internal CP115
+ */
+
+#define CP11X_NAME cp0
+#define CP11X_BASE f2000000
+#define CP11X_PCIEx_MEM_BASE(iface) ((iface == 0) ? 0xc0000000 : \
+ 0xe0000000 + ((iface - 1) * 0x1000000))
+#define CP11X_PCIEx_MEM_SIZE(iface) ((iface == 0) ? 0x1ff00000 : 0xf00000)
+#define CP11X_PCIE0_BASE f2600000
+#define CP11X_PCIE1_BASE f2620000
+#define CP11X_PCIE2_BASE f2640000
+
+#include "armada-cp115.dtsi"
+
+#undef CP11X_NAME
+#undef CP11X_BASE
+#undef CP11X_PCIEx_MEM_BASE
+#undef CP11X_PCIEx_MEM_SIZE
+#undef CP11X_PCIE0_BASE
+#undef CP11X_PCIE1_BASE
+#undef CP11X_PCIE2_BASE
diff --git a/target/linux/mvebu/files/arch/arm64/boot/dts/marvell/puzzle-m901-cn9130-db.dts b/target/linux/mvebu/files/arch/arm64/boot/dts/marvell/puzzle-m901-cn9130-db.dts
new file mode 100644
index 0000000000..16d52c4454
--- /dev/null
+++ b/target/linux/mvebu/files/arch/arm64/boot/dts/marvell/puzzle-m901-cn9130-db.dts
@@ -0,0 +1,241 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (C) 2019 Marvell International Ltd.
+ *
+ * Device tree for the CN9130-DB board.
+ */
+
+#include "puzzle-cn9130.dtsi"
+
+#include <dt-bindings/gpio/gpio.h>
+
+/ {
+ model = "Puzzle-M901";
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+
+ aliases {
+ i2c0 = &cp0_i2c0;
+ ethernet0 = &cp0_eth0;
+ ethernet1 = &cp0_eth1;
+ ethernet2 = &cp0_eth2;
+ gpio1 = &cp0_gpio1;
+ gpio2 = &cp0_gpio2;
+ spi1 = &cp0_spi0;
+ spi2 = &cp0_spi1;
+ serial1 = &cp0_uart0;
+ };
+
+ memory at 00000000 {
+ device_type = "memory";
+ reg = <0x0 0x0 0x0 0x80000000>;
+ };
+
+ ap0_reg_sd_vccq: ap0_sd_vccq at 0 {
+/*
+ compatible = "regulator-gpio";
+ regulator-name = "ap0_sd_vccq";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <3300000>;
+ gpios = <&expander0 8 GPIO_ACTIVE_HIGH>;
+ states = <1800000 0x1 3300000 0x0>;
+*/
+ };
+
+
+
+ cp0_sfp_eth0: sfp-eth at 0 {
+
+ /*
+ * SFP cages are unconnected on early PCBs because of an the I2C
+ * lanes not being connected. Prevent the port for being
+ * unusable by disabling the SFP node.
+ */
+ /* status = "disabled"; */
+ };
+};
+
+&uart0 {
+ status = "okay";
+};
+
+&cp0_uart0 {
+ status = "okay";
+};
+
+/* on-board eMMC - U9 */
+&ap_sdhci0 {
+ pinctrl-names = "default";
+ bus-width = <8>;
+ status = "okay";
+ mmc-ddr-1_8v;
+ mmc-hs400-1_8v;
+ /* vqmmc-supply = <&ap0_reg_sd_vccq>; */
+};
+
+&cp0_crypto {
+ status = "okay";
+};
+
+&cp0_xmdio {
+ status = "okay";
+ phy0: ethernet-phy at 0 {
+ compatible = "ethernet-phy-ieee802.3-c45";
+ reg = <2>;
+ };
+ phy1: ethernet-phy at 1 {
+ compatible = "ethernet-phy-ieee802.3-c45";
+ reg = <0>;
+ };
+ phy2: ethernet-phy at 2 {
+ compatible = "ethernet-phy-ieee802.3-c45";
+ reg = <8>;
+ };
+};
+
+&cp0_ethernet {
+ status = "okay";
+};
+
+/* SLM-1521-V2, CON9 */
+&cp0_eth0 {
+ status = "okay";
+ phy-mode = "2500base-x";
+ phys = <&cp0_comphy2 0>;
+ /* phy = <&phy0>; */
+ managed = "in-band-status";
+};
+
+&cp0_eth1 {
+ status = "okay";
+ phy-mode = "2500base-x";
+ phys = <&cp0_comphy4 1>;
+ /* phy = <&phy1>; */
+ managed = "in-band-status";
+};
+
+&cp0_eth2 {
+ status = "okay";
+ phy-mode = "2500base-x";
+ phys = <&cp0_comphy5 2>;
+ /* phy = <&phy2>; */
+ managed = "in-band-status";
+};
+
+&cp0_gpio1 {
+ status = "okay";
+};
+
+&cp0_gpio2 {
+ status = "okay";
+};
+
+&cp0_i2c0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&cp0_i2c0_pins>;
+ status = "okay";
+ clock-frequency = <100000>;
+ rtc at 32 {
+ compatible = "epson,rx8130";
+ reg = <0x32>;
+ wakeup-source;
+ };
+};
+
+
+/* SLM-1521-V2, CON6 */
+&cp0_pcie0 {
+ status = "okay";
+ num-lanes = <2>;
+ num-viewport = <8>;
+ /* Generic PHY, providing serdes lanes */
+ phys = <&cp0_comphy0 0>, <&cp0_comphy1 0>;
+};
+
+
+
+/* U55 */
+&cp0_spi1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&cp0_spi0_pins>;
+ reg = <0x700680 0x50>, /* control */
+ <0x2000000 0x1000000>; /* CS0 */
+ status = "okay";
+
+ spi-flash at 0 {
+ #address-cells = <0x1>;
+ #size-cells = <0x1>;
+ compatible = "jedec,spi-nor";
+ reg = <0x0>;
+ /* On-board MUX does not allow higher frequencies */
+ spi-max-frequency = <40000000>;
+
+ partitions {
+ compatible = "fixed-partitions";
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ partition at 0 {
+ label = "U-Boot";
+ reg = <0x0 0x1f0000>;
+ };
+ partition at 1f0000 {
+ label = "U-Boot ENV Factory";
+ reg = <0x1f0000 0x10000>;
+ };
+ partition at 200000 {
+ label = "Reserved";
+ reg = <0x200000 0x1f0000>;
+ };
+ partition at 3f0000 {
+ label = "U-Boot ENV";
+ reg = <0x3f0000 0x10000>;
+ };
+
+ };
+ };
+};
+
+&cp0_syscon0 {
+ cp0_pinctrl: pinctrl {
+ compatible = "marvell,cp115-standalone-pinctrl";
+
+ cp0_i2c0_pins: cp0-i2c-pins-0 {
+ marvell,pins = "mpp37", "mpp38";
+ marvell,function = "i2c0";
+ };
+ cp0_i2c1_pins: cp0-i2c-pins-1 {
+ marvell,pins = "mpp35", "mpp36";
+ marvell,function = "i2c1";
+ };
+ cp0_ge1_rgmii_pins: cp0-ge-rgmii-pins-0 {
+ marvell,pins = "mpp0", "mpp1", "mpp2",
+ "mpp3", "mpp4", "mpp5",
+ "mpp6", "mpp7", "mpp8",
+ "mpp9", "mpp10", "mpp11";
+ marvell,function = "ge0";
+ };
+ cp0_ge2_rgmii_pins: cp0-ge-rgmii-pins-1 {
+ marvell,pins = "mpp44", "mpp45", "mpp46",
+ "mpp47", "mpp48", "mpp49",
+ "mpp50", "mpp51", "mpp52",
+ "mpp53", "mpp54", "mpp55";
+ marvell,function = "ge1";
+ };
+ cp0_sdhci_cd_pins: cp0-sdhci-cd-pins-0 {
+ marvell,pins = "mpp43";
+ marvell,function = "gpio";
+ };
+ cp0_sdhci_pins: cp0-sdhi-pins-0 {
+ marvell,pins = "mpp56", "mpp57", "mpp58",
+ "mpp59", "mpp60", "mpp61";
+ marvell,function = "sdio";
+ };
+ cp0_spi0_pins: cp0-spi-pins-0 {
+ marvell,pins = "mpp13", "mpp14", "mpp15", "mpp16";
+ marvell,function = "spi1";
+ };
+ };
+};
\ No newline at end of file
diff --git a/target/linux/mvebu/files/arch/arm64/boot/dts/marvell/puzzle-m901-cn9131-db.dts b/target/linux/mvebu/files/arch/arm64/boot/dts/marvell/puzzle-m901-cn9131-db.dts
new file mode 100644
index 0000000000..d6879613b6
--- /dev/null
+++ b/target/linux/mvebu/files/arch/arm64/boot/dts/marvell/puzzle-m901-cn9131-db.dts
@@ -0,0 +1,182 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (C) 2019 Marvell International Ltd.
+ *
+ * Device tree for the CN9131-DB board.
+ */
+
+#include "puzzle-m901-cn9130-db.dts"
+
+/ {
+ model = "Puzzle-M901";
+ compatible = "marvell,cn9131", "marvell,cn9130",
+ "marvell,armada-ap807-quad", "marvell,armada-ap807";
+
+ aliases {
+ i2c0 = &cp1_i2c0;
+ ethernet3 = &cp1_eth0;
+ ethernet4 = &cp1_eth1;
+ ethernet5 = &cp1_eth2;
+ gpio3 = &cp1_gpio1;
+ gpio4 = &cp1_gpio2;
+ };
+
+ cp1_reg_usb3_vbus0: cp1_usb3_vbus at 0 {
+/*
+ compatible = "regulator-fixed";
+ pinctrl-names = "default";
+ pinctrl-0 = <&cp1_xhci0_vbus_pins>;
+ regulator-name = "cp1-xhci0-vbus";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ enable-active-high;
+ gpio = <&cp1_gpio1 3 GPIO_ACTIVE_HIGH>;
+*/
+ };
+
+ cp1_usb3_0_phy0: cp1_usb3_phy0 {
+/*
+ compatible = "usb-nop-xceiv";
+ vcc-supply = <&cp1_reg_usb3_vbus0>;
+*/
+ };
+
+ cp1_sfp_eth1: sfp-eth1 {
+
+ /*
+ * SFP cages are unconnected on early PCBs because of an the I2C
+ * lanes not being connected. Prevent the port for being
+ * unusable by disabling the SFP node.
+ */
+
+ };
+};
+
+/*
+ * Instantiate the first slave CP115
+ */
+
+#define CP11X_NAME cp1
+#define CP11X_BASE f6000000
+#define CP11X_PCIEx_MEM_BASE(iface) (0xe2000000 + (iface * 0x1000000))
+#define CP11X_PCIEx_MEM_SIZE(iface) 0xf00000
+#define CP11X_PCIE0_BASE f6600000
+#define CP11X_PCIE1_BASE f6620000
+#define CP11X_PCIE2_BASE f6640000
+
+#include "armada-cp115.dtsi"
+
+#undef CP11X_NAME
+#undef CP11X_BASE
+#undef CP11X_PCIEx_MEM_BASE
+#undef CP11X_PCIEx_MEM_SIZE
+#undef CP11X_PCIE0_BASE
+#undef CP11X_PCIE1_BASE
+#undef CP11X_PCIE2_BASE
+
+&cp1_crypto {
+ status = "okay";
+};
+
+&cp1_xmdio {
+ status = "okay";
+ cp1_nbaset_phy0: ethernet-phy at 3 {
+ compatible = "ethernet-phy-ieee802.3-c45";
+ reg = <2>;
+ };
+ cp1_nbaset_phy1: ethernet-phy at 4 {
+ compatible = "ethernet-phy-ieee802.3-c45";
+ reg = <0>;
+ };
+ cp1_nbaset_phy2: ethernet-phy at 5 {
+ compatible = "ethernet-phy-ieee802.3-c45";
+ reg = <8>;
+ };
+};
+
+&cp1_ethernet {
+ status = "okay";
+};
+
+/* CON50 */
+&cp1_eth0 {
+ status = "okay";
+ /* phy = <&cp1_nbaset_phy0>; */
+ phy-mode = "2500base-x";
+ phys = <&cp1_comphy2 0>;
+ managed = "in-band-status";
+};
+
+&cp1_eth1 {
+ status = "okay";
+ /* phy = <&cp1_nbaset_phy1>; */
+ phy-mode = "2500base-x";
+ phys = <&cp1_comphy4 1>;
+ managed = "in-band-status";
+};
+
+&cp1_eth2 {
+ status = "okay";
+ /* phy = <&cp1_nbaset_phy2>; */
+ phy-mode = "2500base-x";
+ phys = <&cp1_comphy5 2>;
+ managed = "in-band-status";
+};
+
+&cp1_sata0 {
+ status = "okay";
+ sata-port at 1 {
+ status = "okay";
+ phys = <&cp1_comphy0 1>;
+ };
+};
+
+&cp1_gpio1 {
+ status = "okay";
+};
+
+&cp1_gpio2 {
+ status = "okay";
+};
+
+&cp1_i2c0 {
+ status = "okay";
+ pinctrl-names = "default";
+ pinctrl-0 = <&cp1_i2c0_pins>;
+ clock-frequency = <100000>;
+};
+
+&cp1_syscon0 {
+ cp1_pinctrl: pinctrl {
+ compatible = "marvell,cp115-standalone-pinctrl";
+
+ cp1_i2c0_pins: cp1-i2c-pins-0 {
+ marvell,pins = "mpp37", "mpp38";
+ marvell,function = "i2c0";
+ };
+ cp1_spi0_pins: cp1-spi-pins-0 {
+ marvell,pins = "mpp13", "mpp14", "mpp15", "mpp16";
+ marvell,function = "spi1";
+ };
+ cp1_xhci0_vbus_pins: cp1-xhci0-vbus-pins {
+ marvell,pins = "mpp3";
+ marvell,function = "gpio";
+ };
+ cp1_sfp_pins: sfp-pins {
+ marvell,pins = "mpp8", "mpp9", "mpp10", "mpp11";
+ marvell,function = "gpio";
+ };
+ cp1_pcie_reset_pins: cp1-pcie-reset-pins {
+ marvell,pins = "mpp0";
+ marvell,function = "gpio";
+ };
+ };
+};
+
+/* CON58 */
+&cp1_usb3_1 {
+ status = "okay";
+ /* usb-phy = <&cp1_usb3_0_phy1>; */
+ phys = <&cp1_comphy3 1>;
+ phy-names = "usb";
+};
\ No newline at end of file
diff --git a/target/linux/mvebu/files/arch/arm64/boot/dts/marvell/puzzle-m902-cn9130-db.dts b/target/linux/mvebu/files/arch/arm64/boot/dts/marvell/puzzle-m902-cn9130-db.dts
new file mode 100644
index 0000000000..9342a535cf
--- /dev/null
+++ b/target/linux/mvebu/files/arch/arm64/boot/dts/marvell/puzzle-m902-cn9130-db.dts
@@ -0,0 +1,261 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (C) 2019 Marvell International Ltd.
+ *
+ * Device tree for the CN9130-DB board.
+ */
+
+#include "puzzle-cn9130.dtsi"
+
+#include <dt-bindings/gpio/gpio.h>
+
+/ {
+ model = "Puzzle-M902";
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+
+ aliases {
+ i2c0 = &cp0_i2c0;
+ ethernet0 = &cp0_eth0;
+ ethernet1 = &cp0_eth1;
+ ethernet2 = &cp0_eth2;
+ gpio1 = &cp0_gpio1;
+ gpio2 = &cp0_gpio2;
+ spi1 = &cp0_spi0;
+ spi2 = &cp0_spi1;
+ serial1 = &cp0_uart0;
+ };
+
+ memory at 00000000 {
+ device_type = "memory";
+ reg = <0x0 0x0 0x0 0x80000000>;
+ };
+
+ ap0_reg_sd_vccq: ap0_sd_vccq at 0 {
+/*
+ compatible = "regulator-gpio";
+ regulator-name = "ap0_sd_vccq";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <3300000>;
+ gpios = <&expander0 8 GPIO_ACTIVE_HIGH>;
+ states = <1800000 0x1 3300000 0x0>;
+*/
+ };
+
+
+ cp0_sfp_eth0: sfp-eth at 0 {
+ /*
+ * SFP cages are unconnected on early PCBs because of an the I2C
+ * lanes not being connected. Prevent the port for being
+ * unusable by disabling the SFP node.
+ */
+ /* status = "disabled"; */
+ };
+};
+
+&uart0 {
+ status = "okay";
+};
+
+&cp0_uart0 {
+ status = "okay";
+};
+
+/* on-board eMMC - U9 */
+&ap_sdhci0 {
+ pinctrl-names = "default";
+ bus-width = <8>;
+ status = "okay";
+ mmc-ddr-1_8v;
+ mmc-hs400-1_8v;
+ /* vqmmc-supply = <&ap0_reg_sd_vccq>;*/
+};
+
+
+&cp0_crypto {
+ status = "okay";
+};
+
+&cp0_xmdio {
+ status = "okay";
+ phy0: ethernet-phy at 0 {
+ compatible = "ethernet-phy-ieee802.3-c45";
+ reg = <2>;
+ };
+ phy1: ethernet-phy at 1 {
+ compatible = "ethernet-phy-ieee802.3-c45";
+ reg = <0>;
+ };
+ phy2: ethernet-phy at 2 {
+ compatible = "ethernet-phy-ieee802.3-c45";
+ reg = <8>;
+ };
+};
+
+&cp0_ethernet {
+ status = "okay";
+};
+
+/* SLM-1521-V2, CON9 */
+&cp0_eth0 {
+ status = "okay";
+ phy-mode = "10gbase-kr";
+ phys = <&cp0_comphy2 0>;
+ /* phy = <&phy0>; */
+ managed = "in-band-status";
+};
+
+&cp0_eth1 {
+ status = "okay";
+ phy-mode = "2500base-x";
+ phys = <&cp0_comphy4 1>;
+ /* phy = <&phy1>; */
+ managed = "in-band-status";
+};
+
+&cp0_eth2 {
+ status = "okay";
+ phy-mode = "2500base-x";
+ phys = <&cp0_comphy1 2>;
+ /* phy = <&phy2>; */
+ managed = "in-band-status";
+};
+
+&cp0_gpio1 {
+ status = "okay";
+};
+
+&cp0_gpio2 {
+ status = "okay";
+};
+
+&cp0_i2c0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&cp0_i2c0_pins>;
+ status = "okay";
+ clock-frequency = <100000>;
+ rtc at 32 {
+ compatible = "epson,rx8130";
+ reg = <0x32>;
+ wakeup-source;
+ };
+};
+
+&cp0_i2c1 {
+ clock-frequency = <100000>;
+};
+
+
+
+/* SLM-1521-V2, CON6 */
+&cp0_sata0 {
+ status = "okay";
+ sata-port at 1 {
+ status = "okay";
+ phys = <&cp0_comphy0 1>;
+ };
+};
+
+&cp0_pcie2 {
+ status = "okay";
+ num-lanes = <1>;
+ num-viewport = <8>;
+ /* Generic PHY, providing serdes lanes */
+ phys = <&cp0_comphy5 2>;
+};
+
+
+
+/* U55 */
+&cp0_spi1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&cp0_spi0_pins>;
+ reg = <0x700680 0x50>, /* control */
+ <0x2000000 0x1000000>; /* CS0 */
+ status = "okay";
+
+ spi-flash at 0 {
+ #address-cells = <0x1>;
+ #size-cells = <0x1>;
+ compatible = "jedec,spi-nor";
+ reg = <0x0>;
+ /* On-board MUX does not allow higher frequencies */
+ spi-max-frequency = <40000000>;
+
+ partitions {
+ compatible = "fixed-partitions";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ partition at 0 {
+ label = "U-Boot";
+ reg = <0x0 0x1f0000>;
+ };
+ partition at 1f0000 {
+ label = "U-Boot ENV Factory";
+ reg = <0x1f0000 0x10000>;
+ };
+ partition at 200000 {
+ label = "Reserved";
+ reg = <0x200000 0x1f0000>;
+ };
+ partition at 3f0000 {
+ label = "U-Boot ENV";
+ reg = <0x3f0000 0x10000>;
+ };
+
+ };
+ };
+};
+
+&cp0_syscon0 {
+ cp0_pinctrl: pinctrl {
+ compatible = "marvell,cp115-standalone-pinctrl";
+
+ cp0_i2c0_pins: cp0-i2c-pins-0 {
+ marvell,pins = "mpp37", "mpp38";
+ marvell,function = "i2c0";
+ };
+ cp0_i2c1_pins: cp0-i2c-pins-1 {
+ marvell,pins = "mpp35", "mpp36";
+ marvell,function = "i2c1";
+ };
+ cp0_ge1_rgmii_pins: cp0-ge-rgmii-pins-0 {
+ marvell,pins = "mpp0", "mpp1", "mpp2",
+ "mpp3", "mpp4", "mpp5",
+ "mpp6", "mpp7", "mpp8",
+ "mpp9", "mpp10", "mpp11";
+ marvell,function = "ge0";
+ };
+ cp0_ge2_rgmii_pins: cp0-ge-rgmii-pins-1 {
+ marvell,pins = "mpp44", "mpp45", "mpp46",
+ "mpp47", "mpp48", "mpp49",
+ "mpp50", "mpp51", "mpp52",
+ "mpp53", "mpp54", "mpp55";
+ marvell,function = "ge1";
+ };
+ cp0_sdhci_cd_pins: cp0-sdhci-cd-pins-0 {
+ marvell,pins = "mpp43";
+ marvell,function = "gpio";
+ };
+ cp0_sdhci_pins: cp0-sdhi-pins-0 {
+ marvell,pins = "mpp56", "mpp57", "mpp58",
+ "mpp59", "mpp60", "mpp61";
+ marvell,function = "sdio";
+ };
+ cp0_spi0_pins: cp0-spi-pins-0 {
+ marvell,pins = "mpp13", "mpp14", "mpp15", "mpp16";
+ marvell,function = "spi1";
+ };
+ };
+};
+
+
+
+&cp0_usb3_1 {
+ status = "okay";
+ /* usb-phy = <&cp0_usb3_0_phy1>; */
+ phys = <&cp0_comphy3 1>;
+ phy-names = "usb";
+};
\ No newline at end of file
diff --git a/target/linux/mvebu/files/arch/arm64/boot/dts/marvell/puzzle-m902-cn9131-db.dts b/target/linux/mvebu/files/arch/arm64/boot/dts/marvell/puzzle-m902-cn9131-db.dts
new file mode 100644
index 0000000000..91816a032a
--- /dev/null
+++ b/target/linux/mvebu/files/arch/arm64/boot/dts/marvell/puzzle-m902-cn9131-db.dts
@@ -0,0 +1,170 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (C) 2019 Marvell International Ltd.
+ *
+ * Device tree for the CN9131-DB board.
+ */
+
+#include "puzzle-m902-cn9130-db.dts"
+
+/ {
+ model = "Puzzle-M902";
+ compatible = "marvell,cn9131", "marvell,cn9130",
+ "marvell,armada-ap807-quad", "marvell,armada-ap807";
+
+ aliases {
+ i2c0 = &cp1_i2c0;
+ ethernet3 = &cp1_eth0;
+ ethernet4 = &cp1_eth1;
+ ethernet5 = &cp1_eth2;
+ gpio3 = &cp1_gpio1;
+ gpio4 = &cp1_gpio2;
+ };
+
+ cp1_reg_usb3_vbus0: cp1_usb3_vbus at 0 {
+/*
+ compatible = "regulator-fixed";
+ pinctrl-names = "default";
+ pinctrl-0 = <&cp1_xhci0_vbus_pins>;
+ regulator-name = "cp1-xhci0-vbus";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ enable-active-high;
+ gpio = <&cp1_gpio1 3 GPIO_ACTIVE_HIGH>;
+*/
+ };
+
+ cp1_usb3_0_phy0: cp1_usb3_phy0 {
+/*
+ compatible = "usb-nop-xceiv";
+ vcc-supply = <&cp1_reg_usb3_vbus0>;
+*/
+ };
+
+ cp1_sfp_eth1: sfp-eth1 {
+
+ /*
+ * SFP cages are unconnected on early PCBs because of an the I2C
+ * lanes not being connected. Prevent the port for being
+ * unusable by disabling the SFP node.
+ */
+ /* status = "disabled"; */
+ };
+};
+
+/*
+ * Instantiate the first slave CP115
+ */
+
+#define CP11X_NAME cp1
+#define CP11X_BASE f4000000
+#define CP11X_PCIEx_MEM_BASE(iface) (0xe2000000 + (iface * 0x1000000))
+#define CP11X_PCIEx_MEM_SIZE(iface) 0xf00000
+#define CP11X_PCIE0_BASE f4600000
+#define CP11X_PCIE1_BASE f4620000
+#define CP11X_PCIE2_BASE f4640000
+
+#include "armada-cp115.dtsi"
+
+#undef CP11X_NAME
+#undef CP11X_BASE
+#undef CP11X_PCIEx_MEM_BASE
+#undef CP11X_PCIEx_MEM_SIZE
+#undef CP11X_PCIE0_BASE
+#undef CP11X_PCIE1_BASE
+#undef CP11X_PCIE2_BASE
+
+&cp1_crypto {
+ status = "okay";
+};
+
+&cp1_xmdio {
+ status = "okay";
+ cp1_nbaset_phy0: ethernet-phy at 3 {
+ compatible = "ethernet-phy-ieee802.3-c45";
+ reg = <2>;
+ };
+ cp1_nbaset_phy1: ethernet-phy at 4 {
+ compatible = "ethernet-phy-ieee802.3-c45";
+ reg = <0>;
+ };
+ cp1_nbaset_phy2: ethernet-phy at 5 {
+ compatible = "ethernet-phy-ieee802.3-c45";
+ reg = <8>;
+ };
+};
+
+&cp1_ethernet {
+ status = "okay";
+};
+
+/* CON50 */
+&cp1_eth0 {
+ status = "okay";
+ /* phy = <&cp1_nbaset_phy0>; */
+ phy-mode = "10gbase-kr";
+ phys = <&cp1_comphy2 0>;
+ managed = "in-band-status";
+};
+
+&cp1_eth1 {
+ status = "okay";
+ /* phy = <&cp1_nbaset_phy1>; */
+ phy-mode = "2500base-x";
+ phys = <&cp1_comphy4 1>;
+ managed = "in-band-status";
+};
+
+&cp1_eth2 {
+ status = "okay";
+ /* phy = <&cp1_nbaset_phy2>;*/
+ phy-mode = "2500base-x";
+ phys = <&cp1_comphy1 2>;
+ managed = "in-band-status";
+};
+
+
+
+&cp1_gpio1 {
+ status = "okay";
+};
+
+&cp1_gpio2 {
+ status = "okay";
+};
+
+&cp1_i2c0 {
+ status = "okay";
+ pinctrl-names = "default";
+ pinctrl-0 = <&cp1_i2c0_pins>;
+ clock-frequency = <100000>;
+};
+
+
+
+&cp1_syscon0 {
+ cp1_pinctrl: pinctrl {
+ compatible = "marvell,cp115-standalone-pinctrl";
+
+ cp1_i2c0_pins: cp1-i2c-pins-0 {
+ marvell,pins = "mpp37", "mpp38";
+ marvell,function = "i2c0";
+ };
+ cp1_spi0_pins: cp1-spi-pins-0 {
+ marvell,pins = "mpp13", "mpp14", "mpp15", "mpp16";
+ marvell,function = "spi1";
+ };
+ cp1_xhci0_vbus_pins: cp1-xhci0-vbus-pins {
+ marvell,pins = "mpp3";
+ marvell,function = "gpio";
+ };
+ cp1_sfp_pins: sfp-pins {
+ marvell,pins = "mpp8", "mpp9", "mpp10", "mpp11";
+ marvell,function = "gpio";
+ };
+ cp1_pcie_reset_pins: cp1-pcie-reset-pins {
+ marvell,pins = "mpp0";
+ marvell,function = "gpio";
+ };
+ };
+};
\ No newline at end of file
diff --git a/target/linux/mvebu/files/arch/arm64/boot/dts/marvell/puzzle-m902-cn9132-db.dts b/target/linux/mvebu/files/arch/arm64/boot/dts/marvell/puzzle-m902-cn9132-db.dts
new file mode 100644
index 0000000000..234143d3b1
--- /dev/null
+++ b/target/linux/mvebu/files/arch/arm64/boot/dts/marvell/puzzle-m902-cn9132-db.dts
@@ -0,0 +1,209 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (C) 2019 Marvell International Ltd.
+ *
+ * Device tree for the CN9132-DB board.
+ */
+
+#include "puzzle-m902-cn9131-db.dts"
+
+/ {
+ model = "Puzzle-M902";
+ compatible = "marvell,cn9132", "marvell,cn9131", "marvell,cn9130",
+ "marvell,armada-ap807-quad", "marvell,armada-ap807";
+
+ aliases {
+ gpio5 = &cp2_gpio1;
+ gpio6 = &cp2_gpio2;
+ ethernet6 = &cp2_eth0;
+ ethernet7 = &cp2_eth1;
+ ethernet8 = &cp2_eth2;
+ };
+
+ cp2_reg_usb3_vbus0: cp2_usb3_vbus at 0 {
+ compatible = "regulator-fixed";
+ regulator-name = "cp2-xhci0-vbus";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ enable-active-high;
+ gpio = <&cp2_gpio1 2 GPIO_ACTIVE_HIGH>;
+ };
+
+ cp2_usb3_0_phy0: cp2_usb3_phy0 {
+ compatible = "usb-nop-xceiv";
+ vcc-supply = <&cp2_reg_usb3_vbus0>;
+ };
+
+ cp2_reg_usb3_vbus1: cp2_usb3_vbus at 1 {
+ compatible = "regulator-fixed";
+ regulator-name = "cp2-xhci1-vbus";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ enable-active-high;
+ gpio = <&cp2_gpio1 3 GPIO_ACTIVE_HIGH>;
+ };
+
+ cp2_usb3_0_phy1: cp2_usb3_phy1 {
+ compatible = "usb-nop-xceiv";
+ vcc-supply = <&cp2_reg_usb3_vbus1>;
+ };
+
+ cp2_reg_sd_vccq: cp2_sd_vccq at 0 {
+ compatible = "regulator-gpio";
+ regulator-name = "cp2_sd_vcc";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <3300000>;
+ gpios = <&cp2_gpio2 17 GPIO_ACTIVE_HIGH>;
+ states = <1800000 0x1 3300000 0x0>;
+ };
+
+ cp2_sfp_eth0: sfp-eth0 {
+ compatible = "sff,sfp";
+ i2c-bus = <&cp2_sfpp0_i2c>;
+ los-gpio = <&cp2_module_expander1 11 GPIO_ACTIVE_HIGH>;
+ mod-def0-gpio = <&cp2_module_expander1 10 GPIO_ACTIVE_LOW>;
+ tx-disable-gpio = <&cp2_module_expander1 9 GPIO_ACTIVE_HIGH>;
+ tx-fault-gpio = <&cp2_module_expander1 8 GPIO_ACTIVE_HIGH>;
+ /*
+ * SFP cages are unconnected on early PCBs because of an the I2C
+ * lanes not being connected. Prevent the port for being
+ * unusable by disabling the SFP node.
+ */
+ status = "disabled";
+ };
+};
+
+/*
+ * Instantiate the second slave CP115
+ */
+
+#define CP11X_NAME cp2
+#define CP11X_BASE f6000000
+#define CP11X_PCIEx_MEM_BASE(iface) (0xe5000000 + (iface * 0x1000000))
+#define CP11X_PCIEx_MEM_SIZE(iface) 0xf00000
+#define CP11X_PCIE0_BASE f6600000
+#define CP11X_PCIE1_BASE f6620000
+#define CP11X_PCIE2_BASE f6640000
+
+#include "armada-cp115.dtsi"
+
+#undef CP11X_NAME
+#undef CP11X_BASE
+#undef CP11X_PCIEx_MEM_BASE
+#undef CP11X_PCIEx_MEM_SIZE
+#undef CP11X_PCIE0_BASE
+#undef CP11X_PCIE1_BASE
+#undef CP11X_PCIE2_BASE
+
+&cp2_crypto {
+ status = "okay";
+};
+
+&cp2_ethernet {
+ status = "okay";
+};
+
+&cp2_xmdio {
+ status = "okay";
+ cp2_nbaset_phy0: ethernet-phy at 6 {
+ compatible = "ethernet-phy-ieee802.3-c45";
+ reg = <2>;
+ };
+ cp2_nbaset_phy1: ethernet-phy at 7 {
+ compatible = "ethernet-phy-ieee802.3-c45";
+ reg = <0>;
+ };
+ cp2_nbaset_phy2: ethernet-phy at 8 {
+ compatible = "ethernet-phy-ieee802.3-c45";
+ reg = <8>;
+ };
+};
+
+/* SLM-1521-V2, CON9 */
+&cp2_eth0 {
+ status = "okay";
+ /* phy = <&cp2_nbaset_phy0>;*/
+ phy-mode = "10gbase-kr";
+ phys = <&cp2_comphy2 0>;
+ managed = "in-band-status";
+};
+
+&cp2_eth1 {
+ status = "okay";
+ /* phy = <&cp2_nbaset_phy1>; */
+ phy-mode = "2500base-x";
+ phys = <&cp2_comphy4 1>;
+ managed = "in-band-status";
+};
+
+&cp2_eth2 {
+ status = "okay";
+ /* phy = <&cp2_nbaset_phy2>;*/
+ phy-mode = "2500base-x";
+ phys = <&cp2_comphy1 2>;
+ managed = "in-band-status";
+};
+
+&cp2_gpio1 {
+ status = "okay";
+};
+
+&cp2_gpio2 {
+ status = "okay";
+};
+
+&cp2_i2c0 {
+ clock-frequency = <100000>;
+
+ /* SLM-1521-V2 - U3 */
+ i2c-mux at 72 {
+ compatible = "nxp,pca9544";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x72>;
+ cp2_sfpp0_i2c: i2c at 0 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0>;
+ };
+
+ i2c at 1 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <1>;
+ /* U12 */
+ cp2_module_expander1: pca9555 at 21 {
+ compatible = "nxp,pca9555";
+ pinctrl-names = "default";
+ gpio-controller;
+ #gpio-cells = <2>;
+ reg = <0x21>;
+ };
+ };
+ };
+};
+
+/* CON 2 on SLM-1683 - microSD */
+&cp2_sdhci0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&cp2_sdhci_pins>;
+ bus-width = <4>;
+ cd-gpios = <&cp2_gpio2 23 GPIO_ACTIVE_LOW>;
+ vqmmc-supply = <&cp2_reg_sd_vccq>;
+};
+
+&cp2_syscon0 {
+ cp2_pinctrl: pinctrl {
+ compatible = "marvell,cp115-standalone-pinctrl";
+
+ cp2_i2c0_pins: cp2-i2c-pins-0 {
+ marvell,pins = "mpp37", "mpp38";
+ marvell,function = "i2c0";
+ };
+ cp2_sdhci_pins: cp2-sdhi-pins-0 {
+ marvell,pins = "mpp56", "mpp57", "mpp58",
+ "mpp59", "mpp60", "mpp61";
+ marvell,function = "sdio";
+ };
+ };
+};
\ No newline at end of file
diff --git a/target/linux/mvebu/image/cortexa72.mk b/target/linux/mvebu/image/cortexa72.mk
index 1440c07a0b..c04ad2ae9e 100644
--- a/target/linux/mvebu/image/cortexa72.mk
+++ b/target/linux/mvebu/image/cortexa72.mk
@@ -43,3 +43,27 @@ define Device/marvell_macchiatobin-singleshot
SUPPORTED_DEVICES := marvell,armada8040-mcbin-singleshot
endef
TARGET_DEVICES += marvell_macchiatobin-singleshot
+
+define Device/marvell_puzzle-m901-cn9131-db
+ $(call Device/Default-arm64)
+ DEVICE_VENDOR := iEi
+ DEVICE_MODEL := Puzzle-M901
+ DEVICE_DTS := puzzle-m901-cn9131-db
+ IMAGE/sdcard.img.gz := boot-img-ext4 | sdcard-img-ext4 | gzip | append-metadata
+ IMAGES += factory.bin
+ IMAGE/factory.bin := append-kernel | pad-to 64k
+ SUPPORTED_DEVICES :=marvell,cn9131 marvell,puzzle-m901-cn9131-db
+endef
+TARGET_DEVICES += marvell_puzzle-m901-cn9131-db
+
+define Device/marvell_puzzle-m902-cn9132-db
+ $(call Device/Default-arm64)
+ DEVICE_VENDOR := iEi
+ DEVICE_MODEL := Puzzle-M902
+ DEVICE_DTS := puzzle-m902-cn9132-db
+ IMAGE/sdcard.img.gz := boot-img-ext4 | sdcard-img-ext4 | gzip | append-metadata
+ IMAGES += factory.bin
+ IMAGE/factory.bin := append-kernel | pad-to 64k
+ SUPPORTED_DEVICES :=marvell,cn9132 marvell,puzzle-m902-cn9132-db
+endef
+TARGET_DEVICES += marvell_puzzle-m902-cn9132-db
--
2.17.1
More information about the openwrt-devel
mailing list