[PATCH 3/3] ramips: add RT6855A SoC Linux support patches
Chuanhong Guo
gch981213 at gmail.com
Sun Dec 27 09:08:58 EST 2020
Hi!
On Sun, Dec 27, 2020 at 8:49 PM Rafaël Carré <funman at videolan.org> wrote:
> Thanks for the explanation.
>
> I had a look at the datasheet, also at the commits log of spi-mt7621.c.
> This also explains why I had to use dd bs=32 to get correct MTD reads.
>
> I am still a bit confused by the difference between chipselect and
> slaveselect.
>
> On my target "rs_slave_sel" needs to have value "0 (default is flash)"
> to be able to read flash.
>
> https://en.wikipedia.org/wiki/Chip_select starts with "Chip select (CS)
> or slave select (SS)" so they can be synonymous. I guess in this case
> the rs_slave_sel does something different from toggling the chipselect
> pin of the (flash) SPI slave.
They are the same thing. If you have to set it to 0, that probably
means...
> I also tried different values of cs_polar in SPI_CS_POLAR, but they
> don't seem to have any effect, the flash can always be read as long as
> rs_slave_sel stays 0.
... there may not be a SPI_CS_POLAR on RT6855A. And you
have to live with that transfer size limitation unfortunately.
> I am not sure what else to try or where to look at.
> Should I try a different version of vendor driver (bbu_spiflash.c)
> maybe, to gather some more informations on this rt6855a SoC ?
As you can't trick the hardware to control chipselect, there isn't much
in current spi-mt7621.c for you to reuse. You need to write a
new spi driver to use the controller as a spi flash controller
with limited transfer capability, using spi-mem interface available
since linux v4.18.
> Another thing, I noticed "master->num_chipselect = 2;" in the driver,
> is there a reason for this limit, rather than 8 as rs_slave_sel is 3
> bits? (or 7 to keep device 7 as non-existent) ?
This controller was known to be used on mt7621/mt76x8 only.
Both mt7621 and mt7628 only have 2 chipselect pins exposed.
As it's unlikely to be used on any other new SoCs, it's filled with
the actual available chipselects, which is 2.
--
Regards,
Chuanhong Guo
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