[PATCH] wap300n
Rafaël Carré
funman at videolan.org
Tue Dec 22 14:27:56 EST 2020
---
target/linux/ramips/Makefile | 2 +-
target/linux/ramips/dts/rt6855.dtsi | 93 +
.../ramips/dts/rt6855a_linksys_wap300n.dts | 18 +
.../files/drivers/net/ethernet/ralink/Kconfig | 6 +-
.../drivers/net/ethernet/ralink/Makefile | 1 +
.../drivers/net/ethernet/ralink/esw_rt3050.c | 22 +-
.../drivers/net/ethernet/ralink/mtk_eth_soc.c | 4 +-
.../drivers/net/ethernet/ralink/mtk_eth_soc.h | 1 +
.../drivers/net/ethernet/ralink/soc_rt6855.c | 102 +
target/linux/ramips/image/Makefile | 1 +
target/linux/ramips/image/rt6855a.mk | 15 +
.../patches-5.4/333-MIPS-ralink-rt6855a.patch | 3142 +++++++++++++++++
.../rt6855a/base-files/etc/board.d/01_leds | 12 +
.../rt6855a/base-files/etc/board.d/02_network | 11 +
.../base-files/etc/board.d/03_gpio_switches | 11 +
target/linux/ramips/rt6855a/config-5.4 | 2531 +++++++++++++
.../ramips/rt6855a/profiles/00-default.mk | 17 +
target/linux/ramips/rt6855a/target.mk | 15 +
18 files changed, 5999 insertions(+), 5 deletions(-)
create mode 100644 target/linux/ramips/dts/rt6855.dtsi
create mode 100644 target/linux/ramips/dts/rt6855a_linksys_wap300n.dts
create mode 100644 target/linux/ramips/files/drivers/net/ethernet/ralink/soc_rt6855.c
create mode 100644 target/linux/ramips/image/rt6855a.mk
create mode 100644 target/linux/ramips/patches-5.4/333-MIPS-ralink-rt6855a.patch
create mode 100755 target/linux/ramips/rt6855a/base-files/etc/board.d/01_leds
create mode 100755 target/linux/ramips/rt6855a/base-files/etc/board.d/02_network
create mode 100755 target/linux/ramips/rt6855a/base-files/etc/board.d/03_gpio_switches
create mode 100644 target/linux/ramips/rt6855a/config-5.4
create mode 100644 target/linux/ramips/rt6855a/profiles/00-default.mk
create mode 100644 target/linux/ramips/rt6855a/target.mk
diff --git a/target/linux/ramips/Makefile b/target/linux/ramips/Makefile
index c3d118b2ab..f03118c1aa 100644
--- a/target/linux/ramips/Makefile
+++ b/target/linux/ramips/Makefile
@@ -9,7 +9,7 @@ include $(TOPDIR)/rules.mk
ARCH:=mipsel
BOARD:=ramips
BOARDNAME:=MediaTek Ralink MIPS
-SUBTARGETS:=mt7620 mt7621 mt76x8 rt288x rt305x rt3883
+SUBTARGETS:=mt7620 mt7621 mt76x8 rt288x rt305x rt3883 rt6855a
FEATURES:=squashfs gpio
KERNEL_PATCHVER:=5.4
diff --git a/target/linux/ramips/dts/rt6855.dtsi b/target/linux/ramips/dts/rt6855.dtsi
new file mode 100644
index 0000000000..4ff9460256
--- /dev/null
+++ b/target/linux/ramips/dts/rt6855.dtsi
@@ -0,0 +1,93 @@
+// SPDX-License-Identifier: GPL-2.0
+/ {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "ralink,rt6855-soc";
+
+ cpus {
+ cpu at 0 {
+ compatible = "mips,mips34Kc";
+ };
+ };
+
+ cpuintc: cpuintc {
+ #address-cells = <0>;
+ #interrupt-cells = <1>;
+ interrupt-controller;
+ compatible = "mti,cpu-interrupt-controller";
+ };
+
+ palmbus at 1fb00000 {
+ compatible = "palmbus";
+ reg = <0x1fb00000 0xe0000>;
+ ranges = <0x0 0x1fb00000 0x100000>;
+
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ sysc at 0 {
+ compatible = "ralink,rt6855-sysc";
+ reg = <0x0 0x100>;
+ };
+
+ intc: intc at 40000 {
+ compatible = "ralink,rt6855-intc";
+ reg = <0x40000 0x100>;
+
+ interrupt-controller;
+ #interrupt-cells = <1>;
+
+ interrupt-parent = <&cpuintc>;
+ };
+
+ memc at 300 {
+ compatible = "ralink,rt6855-memc", "ralink,rt3050-memc";
+ reg = <0x300 0x100>;
+ };
+
+ watchdog at f0100 {
+ compatible = "ralink,rt6855-wdt";
+ reg = <0xf0100 0x10>;
+ };
+
+ uart: uart at f0000 {
+ compatible = "ns8250";
+ reg = <0xf0000 0x30>;
+ interrupts = <0>;
+
+ clock-frequency = <921600>;
+
+ reg-io-width = <4>;
+ reg-shift = <2>;
+ no-loopback-test;
+
+ status = "okay";
+
+ interrupt-parent = <&intc>;
+ };
+
+ gdma: gdma at 30000 {
+ compatible = "ralink,gdma-rt2880";
+ reg = <0x30000 0x100>;
+ };
+
+ ethernet: ethernet at 50000{
+ compatible = "ralink,rt6855-eth";
+ reg = <0x50000 0x10000>;
+
+ interrupt-parent = <&intc>;
+ interrupts = <21>;
+
+ mediatek,switch = <&esw>;
+ };
+
+ esw: esw at 60000 {
+ compatible = "ralink,rt3050-esw";
+ reg = <0x60000 0x8000>;
+
+ interrupt-parent = <&intc>;
+ interrupts = <15>;
+ };
+
+ };
+};
diff --git a/target/linux/ramips/dts/rt6855a_linksys_wap300n.dts b/target/linux/ramips/dts/rt6855a_linksys_wap300n.dts
new file mode 100644
index 0000000000..d923946c4a
--- /dev/null
+++ b/target/linux/ramips/dts/rt6855a_linksys_wap300n.dts
@@ -0,0 +1,18 @@
+// SPDX-License-Identifier: GPL-2.0
+/dts-v1/;
+
+/include/ "rt6855.dtsi"
+
+/ {
+ compatible = "ralink,rt6855-soc";
+ model = "Linksys WAP300n";
+
+ memory at 0 {
+ device_type = "memory";
+ reg = <0x20000 0x3fe0000>;
+ };
+
+ chosen {
+ bootargs = "console=ttyS0,57600";
+ };
+};
diff --git a/target/linux/ramips/files/drivers/net/ethernet/ralink/Kconfig b/target/linux/ramips/files/drivers/net/ethernet/ralink/Kconfig
index 26e5e6d73e..f34ab148b1 100644
--- a/target/linux/ramips/files/drivers/net/ethernet/ralink/Kconfig
+++ b/target/linux/ramips/files/drivers/net/ethernet/ralink/Kconfig
@@ -11,6 +11,10 @@ if NET_RALINK_SOC
choice
prompt "MAC type"
+config NET_RALINK_RT6855
+ bool "RT6855"
+ depends on MIPS && SOC_RT6855
+
config NET_RALINK_RT2880
bool "RT2882"
depends on MIPS && SOC_RT288X
@@ -50,7 +54,7 @@ config NET_RALINK_MDIO_MT7620
config NET_RALINK_ESW_RT3050
def_tristate NET_RALINK_SOC
- depends on NET_RALINK_RT3050
+ depends on NET_RALINK_RT3050 || NET_RALINK_RT6855
config NET_RALINK_GSW_MT7620
def_tristate NET_RALINK_SOC
diff --git a/target/linux/ramips/files/drivers/net/ethernet/ralink/Makefile b/target/linux/ramips/files/drivers/net/ethernet/ralink/Makefile
index 79d2dbfef9..bbb4fb3609 100644
--- a/target/linux/ramips/files/drivers/net/ethernet/ralink/Makefile
+++ b/target/linux/ramips/files/drivers/net/ethernet/ralink/Makefile
@@ -12,6 +12,7 @@ ralink-eth-$(CONFIG_NET_RALINK_RT2880) += soc_rt2880.o
ralink-eth-$(CONFIG_NET_RALINK_RT3050) += soc_rt3050.o
ralink-eth-$(CONFIG_NET_RALINK_RT3883) += soc_rt3883.o
ralink-eth-$(CONFIG_NET_RALINK_MT7620) += soc_mt7620.o
+ralink-eth-$(CONFIG_NET_RALINK_RT6855) += soc_rt6855.o
obj-$(CONFIG_NET_RALINK_ESW_RT3050) += esw_rt3050.o
obj-$(CONFIG_NET_RALINK_GSW_MT7620) += gsw_mt7620.o mt7530.o
diff --git a/target/linux/ramips/files/drivers/net/ethernet/ralink/esw_rt3050.c b/target/linux/ramips/files/drivers/net/ethernet/ralink/esw_rt3050.c
index 292f11a170..f5b4f59170 100644
--- a/target/linux/ramips/files/drivers/net/ethernet/ralink/esw_rt3050.c
+++ b/target/linux/ramips/files/drivers/net/ethernet/ralink/esw_rt3050.c
@@ -85,6 +85,7 @@
#define RT305X_ESW_PCR0_WT_NWAY_DATA_S 16
#define RT305X_ESW_PCR0_WT_PHY_CMD BIT(13)
#define RT305X_ESW_PCR0_CPU_PHY_REG_S 8
+#define RT305X_ESW_PCR0_WT_DONE BIT(31)
#define RT305X_ESW_PCR1_WT_DONE BIT(0)
@@ -271,8 +272,13 @@ static u32 rt305x_mii_write(struct rt305x_esw *esw, u32 phy_addr,
int ret = 0;
while (1) {
+#ifdef CONFIG_SOC_RT6855
+ if (!(esw_r32(esw, RT305X_ESW_REG_PCR0) &
+ RT305X_ESW_PCR0_WT_DONE))
+#else
if (!(esw_r32(esw, RT305X_ESW_REG_PCR1) &
RT305X_ESW_PCR1_WT_DONE))
+#endif
break;
if (time_after(jiffies, t_start + RT305X_ESW_PHY_TIMEOUT)) {
ret = 1;
@@ -281,15 +287,27 @@ static u32 rt305x_mii_write(struct rt305x_esw *esw, u32 phy_addr,
}
write_data &= 0xffff;
+#ifdef CONFIG_SOC_RT6855
+ esw_w32(esw, (write_data ) | (phy_register << 16) | (phy_addr << 24) | (1 << 30),
+ RT305X_ESW_REG_PCR0);
+ esw_w32(esw, (write_data ) | (phy_register << 16) | (phy_addr << 24) | (3 << 30),
+ RT305X_ESW_REG_PCR0);
+#else
esw_w32(esw, (write_data << RT305X_ESW_PCR0_WT_NWAY_DATA_S) |
(phy_register << RT305X_ESW_PCR0_CPU_PHY_REG_S) |
(phy_addr) | RT305X_ESW_PCR0_WT_PHY_CMD,
RT305X_ESW_REG_PCR0);
+#endif
t_start = jiffies;
while (1) {
- if (esw_r32(esw, RT305X_ESW_REG_PCR1) &
- RT305X_ESW_PCR1_WT_DONE)
+#ifdef CONFIG_SOC_RT6855
+ if (!(esw_r32(esw, RT305X_ESW_REG_PCR0) &
+ RT305X_ESW_PCR0_WT_DONE))
+#else
+ if (!(esw_r32(esw, RT305X_ESW_REG_PCR1) &
+ RT305X_ESW_PCR1_WT_DONE))
+#endif
break;
if (time_after(jiffies, t_start + RT305X_ESW_PHY_TIMEOUT)) {
diff --git a/target/linux/ramips/files/drivers/net/ethernet/ralink/mtk_eth_soc.c b/target/linux/ramips/files/drivers/net/ethernet/ralink/mtk_eth_soc.c
index f8301ad3ca..d731b4d83b 100644
--- a/target/linux/ramips/files/drivers/net/ethernet/ralink/mtk_eth_soc.c
+++ b/target/linux/ramips/files/drivers/net/ethernet/ralink/mtk_eth_soc.c
@@ -1085,7 +1085,7 @@ poll_again:
return rx_done;
}
-static void fe_tx_timeout(struct net_device *dev)
+static void fe_tx_timeout(struct net_device *dev/*, unsigned int txqueue*/)
{
struct fe_priv *priv = netdev_priv(dev);
struct fe_tx_ring *ring = &priv->tx_ring;
@@ -1355,6 +1355,7 @@ static int __init fe_init(struct net_device *dev)
struct device_node *port;
const char *mac_addr;
int err;
+// const char mac[] = { 0x58, 0xef, 0x68, 0xc7, 0x51, 0xbb };
priv->soc->reset_fe();
@@ -1367,6 +1368,7 @@ static int __init fe_init(struct net_device *dev)
fe_reset_phy(priv);
mac_addr = of_get_mac_address(priv->dev->of_node);
+// mac_addr = mac;
if (!IS_ERR_OR_NULL(mac_addr))
ether_addr_copy(dev->dev_addr, mac_addr);
diff --git a/target/linux/ramips/files/drivers/net/ethernet/ralink/mtk_eth_soc.h b/target/linux/ramips/files/drivers/net/ethernet/ralink/mtk_eth_soc.h
index 00f1a0e7e6..19f0dacaa5 100644
--- a/target/linux/ramips/files/drivers/net/ethernet/ralink/mtk_eth_soc.h
+++ b/target/linux/ramips/files/drivers/net/ethernet/ralink/mtk_eth_soc.h
@@ -294,6 +294,7 @@ enum fe_work_flag {
#define FE_PDMA_SIZE_4DWORDS (0 << 4)
#define FE_PDMA_SIZE_8DWORDS (1 << 4)
#define FE_PDMA_SIZE_16DWORDS (2 << 4)
+#define FE_PDMA_SIZE_32DWORDS (3 << 4)
#define FE_US_CYC_CNT_MASK 0xff
#define FE_US_CYC_CNT_SHIFT 0x8
diff --git a/target/linux/ramips/files/drivers/net/ethernet/ralink/soc_rt6855.c b/target/linux/ramips/files/drivers/net/ethernet/ralink/soc_rt6855.c
new file mode 100644
index 0000000000..2743a41e9f
--- /dev/null
+++ b/target/linux/ramips/files/drivers/net/ethernet/ralink/soc_rt6855.c
@@ -0,0 +1,102 @@
+/* This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * Copyright (C) 2009-2015 John Crispin <blogic at openwrt.org>
+ * Copyright (C) 2009-2015 Felix Fietkau <nbd at nbd.name>
+ * Copyright (C) 2013-2015 Michael Lee <igvtee at gmail.com>
+ */
+
+#include <linux/module.h>
+
+#include <asm/mach-ralink/ralink_regs.h>
+
+#include "mtk_eth_soc.h"
+#include "mdio_rt2880.h"
+
+static const u16 rt5350_reg_table[FE_REG_COUNT] = {
+ [FE_REG_PDMA_GLO_CFG] = RT5350_PDMA_GLO_CFG, // OK
+ [FE_REG_PDMA_RST_CFG] = RT5350_PDMA_RST_CFG, // RST_IDX
+ [FE_REG_DLY_INT_CFG] = RT5350_DLY_INT_CFG, // OK
+ [FE_REG_TX_BASE_PTR0] = RT5350_TX_BASE_PTR0,
+ [FE_REG_TX_MAX_CNT0] = RT5350_TX_MAX_CNT0,
+ [FE_REG_TX_CTX_IDX0] = RT5350_TX_CTX_IDX0,
+ [FE_REG_TX_DTX_IDX0] = RT5350_TX_DTX_IDX0,
+ [FE_REG_RX_BASE_PTR0] = RT5350_RX_BASE_PTR0,
+ [FE_REG_RX_MAX_CNT0] = RT5350_RX_MAX_CNT0,
+ [FE_REG_RX_CALC_IDX0] = RT5350_RX_CALC_IDX0,
+ [FE_REG_RX_DRX_IDX0] = RT5350_RX_DRX_IDX0,
+ [FE_REG_FE_INT_ENABLE] = RT5350_FE_INT_ENABLE, // OK
+ [FE_REG_FE_INT_STATUS] = RT5350_FE_INT_STATUS, // OK
+ [FE_REG_FE_RST_GL] = 0,
+ [FE_REG_FE_DMA_VID_BASE] = 0,
+};
+
+static void rt5350_init_data(struct fe_soc_data *data,
+ struct net_device *netdev)
+{
+ struct fe_priv *priv = netdev_priv(netdev);
+
+ priv->flags = FE_FLAG_HAS_SWITCH;
+ netdev->hw_features = NETIF_F_SG | NETIF_F_RXCSUM;
+}
+
+static void rt5350_set_mac(struct fe_priv *priv, unsigned char *mac)
+{
+ unsigned long flags;
+
+ spin_lock_irqsave(&priv->page_lock, flags);
+ fe_w32((mac[0] << 8) | mac[1], RT5350_SDM_MAC_ADRH);
+ fe_w32((mac[2] << 24) | (mac[3] << 16) | (mac[4] << 8) | mac[5],
+ RT5350_SDM_MAC_ADRL);
+ spin_unlock_irqrestore(&priv->page_lock, flags);
+}
+
+static void rt5350_rxcsum_config(bool enable)
+{
+ if (enable)
+ fe_w32(fe_r32(RT5350_SDM_CFG) | (RT5350_SDM_ICS_EN |
+ RT5350_SDM_TCS_EN | RT5350_SDM_UCS_EN),
+ RT5350_SDM_CFG);
+ else
+ fe_w32(fe_r32(RT5350_SDM_CFG) & ~(RT5350_SDM_ICS_EN |
+ RT5350_SDM_TCS_EN | RT5350_SDM_UCS_EN),
+ RT5350_SDM_CFG);
+}
+
+static int rt5350_fwd_config(struct fe_priv *priv)
+{
+ struct net_device *dev = priv_netdev(priv);
+
+ rt5350_rxcsum_config((dev->features & NETIF_F_RXCSUM));
+
+ return 0;
+}
+
+static void rt5350_fe_reset(void)
+{
+}
+
+static struct fe_soc_data rt5350_data = {
+ .init_data = rt5350_init_data,
+ .reg_table = rt5350_reg_table,
+ .reset_fe = rt5350_fe_reset,
+ .set_mac = rt5350_set_mac,
+ .fwd_config = rt5350_fwd_config,
+ .pdma_glo_cfg = FE_PDMA_SIZE_32DWORDS,
+ .checksum_bit = RX_DMA_L4VALID,
+ .rx_int = RT5350_RX_DONE_INT,
+ .tx_int = RT5350_TX_DONE_INT,
+};
+
+const struct of_device_id of_fe_match[] = {
+ { .compatible = "ralink,rt6855-eth", .data = &rt5350_data },
+ {},
+};
+
+MODULE_DEVICE_TABLE(of, of_fe_match);
diff --git a/target/linux/ramips/image/Makefile b/target/linux/ramips/image/Makefile
index 309ccbdf90..a3ba2561e9 100644
--- a/target/linux/ramips/image/Makefile
+++ b/target/linux/ramips/image/Makefile
@@ -17,6 +17,7 @@ DEVICE_VARS += SERCOMM_PAD JCG_MAXSIZE
loadaddr-y := 0x80000000
loadaddr-$(CONFIG_TARGET_ramips_rt288x) := 0x88000000
loadaddr-$(CONFIG_TARGET_ramips_mt7621) := 0x80001000
+loadaddr-$(CONFIG_TARGET_ramips_rt6855a) := 0x80020000
ldrplatform-y := ralink
ldrplatform-$(CONFIG_TARGET_ramips_mt7621) := mt7621
diff --git a/target/linux/ramips/image/rt6855a.mk b/target/linux/ramips/image/rt6855a.mk
new file mode 100644
index 0000000000..8e622ce55e
--- /dev/null
+++ b/target/linux/ramips/image/rt6855a.mk
@@ -0,0 +1,15 @@
+#
+# RT6855A Profiles
+#
+
+DEVICE_VARS += DLINK_ROM_ID DLINK_FAMILY_MEMBER DLINK_FIRMWARE_SIZE DLINK_IMAGE_OFFSET
+
+define Device/linksys_wap300n
+ SOC := rt6855a
+ IMAGE_SIZE := 7936k
+ DEVICE_VENDOR := Linksys
+ DEVICE_MODEL := WAP300N
+ DEVICE_PACKAGES:= kmod-rt2800-pci
+ SUPPORTED_DEVICES += wap300n
+endef
+TARGET_DEVICES += linksys_wap300n
diff --git a/target/linux/ramips/patches-5.4/333-MIPS-ralink-rt6855a.patch b/target/linux/ramips/patches-5.4/333-MIPS-ralink-rt6855a.patch
new file mode 100644
index 0000000000..eae73853d0
--- /dev/null
+++ b/target/linux/ramips/patches-5.4/333-MIPS-ralink-rt6855a.patch
@@ -0,0 +1,3142 @@
+From a19bf23f4a1ead2dfd353eb108110744ce8d768a Mon Sep 17 00:00:00 2001
+From: =?UTF-8?q?Rafa=C3=ABl=20Carr=C3=A9?= <funman at videolan.org>
+Date: Sat, 19 Dec 2020 14:35:15 +0100
+Subject: [PATCH] wap300n
+
+---
+ arch/mips/boot/dts/ralink/Makefile | 1 +
+ arch/mips/boot/dts/ralink/rt6855.dtsi | 197 +++
+ arch/mips/boot/dts/ralink/wap300n.dts | 23 +
+ .../include/asm/mach-ralink/ralink_regs.h | 1 +
+ arch/mips/pci/Makefile | 1 +
+ arch/mips/pci/pci-legacy.c | 15 +-
+ arch/mips/pci/pci-rt3883.c | 93 +-
+ arch/mips/ralink/Kconfig | 13 +-
+ arch/mips/ralink/Makefile | 6 +-
+ arch/mips/ralink/Platform | 5 +
+ arch/mips/ralink/early_printk.c | 5 +-
+ arch/mips/ralink/eureka_ep430.h | 186 +++
+ arch/mips/ralink/irq-rt6855.c | 171 +++
+ arch/mips/ralink/pci.c | 1067 +++++++++++++++++
+ arch/mips/ralink/reset.c | 24 +-
+ arch/mips/ralink/rt6855.c | 55 +
+ arch/mips/ralink/rt_mmap.h | 551 +++++++++
+ drivers/char/Makefile | 1 +
+ .../net/wireless/ralink/rt2x00/rt2800pci.c | 51 +
+ drivers/spi/spi-mt7621.c | 14 +-
+ drivers/watchdog/Kconfig | 7 +
+ drivers/watchdog/Makefile | 1 +
+ drivers/watchdog/rt6855_wdt.c | 177 +++
+ kernel/dma/direct.c | 1 +
+ scripts/Makefile | 4 +-
+ 25 files changed, 2642 insertions(+), 28 deletions(-)
+ create mode 100644 arch/mips/boot/dts/ralink/rt6855.dtsi
+ create mode 100644 arch/mips/boot/dts/ralink/wap300n.dts
+ create mode 100755 arch/mips/ralink/eureka_ep430.h
+ create mode 100644 arch/mips/ralink/irq-rt6855.c
+ create mode 100644 arch/mips/ralink/pci.c
+ create mode 100644 arch/mips/ralink/rt6855.c
+ create mode 100644 arch/mips/ralink/rt_mmap.h
+ create mode 100644 drivers/watchdog/rt6855_wdt.c
+
+diff --git a/arch/mips/boot/dts/ralink/Makefile b/arch/mips/boot/dts/ralink/Makefile
+index 6c26dfa0a903..08c612190936 100644
+--- a/arch/mips/boot/dts/ralink/Makefile
++++ b/arch/mips/boot/dts/ralink/Makefile
+@@ -3,6 +3,7 @@ dtb-$(CONFIG_DTB_RT2880_EVAL) += rt2880_eval.dtb
+ dtb-$(CONFIG_DTB_RT305X_EVAL) += rt3052_eval.dtb
+ dtb-$(CONFIG_DTB_RT3883_EVAL) += rt3883_eval.dtb
+ dtb-$(CONFIG_DTB_MT7620A_EVAL) += mt7620a_eval.dtb
++dtb-$(CONFIG_DTB_WAP300N) += wap300n.dtb
+ dtb-$(CONFIG_DTB_OMEGA2P) += omega2p.dtb
+ dtb-$(CONFIG_DTB_VOCORE2) += vocore2.dtb
+
+diff --git a/arch/mips/boot/dts/ralink/rt6855.dtsi b/arch/mips/boot/dts/ralink/rt6855.dtsi
+new file mode 100644
+index 000000000000..f02b52ee5d06
+--- /dev/null
++++ b/arch/mips/boot/dts/ralink/rt6855.dtsi
+@@ -0,0 +1,197 @@
++// SPDX-License-Identifier: GPL-2.0
++/ {
++ #address-cells = <1>;
++ #size-cells = <1>;
++ compatible = "ralink,rt6855-soc";
++
++ cpus {
++ cpu at 0 {
++ compatible = "mips,mips34Kc";
++ };
++ };
++
++ cpuintc: cpuintc {
++ #address-cells = <0>;
++ #interrupt-cells = <1>;
++ interrupt-controller;
++ compatible = "mti,cpu-interrupt-controller";
++ };
++
++ palmbus at 1fb00000 {
++ compatible = "palmbus";
++ reg = <0x1fb00000 0xe0000>;
++ ranges = <0x0 0x1fb00000 0x100000>;
++
++ #address-cells = <1>;
++ #size-cells = <1>;
++
++ sysc at 0 {
++ compatible = "ralink,rt6855-sysc";
++ reg = <0x0 0x100>;
++ };
++
++ intc: intc at 40000 {
++ compatible = "ralink,rt6855-intc";
++ reg = <0x40000 0x100>;
++
++ interrupt-controller;
++ #interrupt-cells = <1>;
++
++ interrupt-parent = <&cpuintc>;
++ };
++
++ memc at 300 {
++ compatible = "ralink,rt6855-memc", "ralink,rt3050-memc";
++ reg = <0x300 0x100>;
++ };
++
++ watchdog at f0100 {
++ compatible = "ralink,rt6855-wdt";
++ reg = <0xf0100 0x10>;
++ };
++
++ uart: uart at f0000 {
++ compatible = "ns8250";
++ reg = <0xf0000 0x30>;
++ interrupts = <0>;
++
++ clock-frequency = <921600>;
++
++ reg-io-width = <4>;
++ reg-shift = <2>;
++ no-loopback-test;
++
++ status = "okay";
++
++ interrupt-parent = <&intc>;
++ };
++
++ gdma: gdma at 30000 {
++ compatible = "ralink,gdma-rt2880";
++ reg = <0x30000 0x100>;
++ };
++
++ ethernet: ethernet at 50000{
++ compatible = "ralink,rt6855-eth";
++ reg = <0x50000 0x10000>;
++
++ interrupt-parent = <&intc>;
++ interrupts = <21>;
++
++ mediatek,switch = <&esw>;
++ mtd-mac-address = <&factory 0xe000>;
++ };
++
++ esw: esw at 60000 {
++ compatible = "ralink,rt3050-esw";
++ reg = <0x60000 0x8000>;
++
++ interrupt-parent = <&intc>;
++ interrupts = <15>;
++ };
++
++ spi0: spi at c0b00 {
++ status = "disabled";
++
++ compatible = "ralink,mt7621-spi";
++ reg = <0xc0b00 0x100>;
++
++ //clocks = <&pll MT7621_CLK_BUS>;
++
++ //resets = <&rstctrl 18>;
++ //reset-names = "spi";
++
++ #address-cells = <1>;
++ #size-cells = <0>;
++
++ //pinctrl-names = "default";
++ //pinctrl-0 = <&spi_pins>;
++ };
++ };
++
++ pci: pci at 1fb80000 {
++ compatible = "ralink,rt3883-pci";
++ reg = <0x1fb80000 0x20000>;
++ #address-cells = <1>;
++ #size-cells = <1>;
++ ranges; /* direct mapping */
++
++ status = "disabled";
++
++ pciintc: interrupt-controller {
++ interrupt-controller;
++ #address-cells = <0>;
++ #interrupt-cells = <1>;
++
++ interrupt-parent = <&cpuintc>;
++ interrupts = <4>;
++ };
++
++ pci at 0 {
++ #address-cells = <3>;
++ #size-cells = <2>;
++ #interrupt-cells = <1>;
++
++ device_type = "pci";
++
++ bus-range = <0 1>;
++ ranges = <
++ 0x02000000 0 0x00000000 0x20000000 0 0x10000000 /* pci memory */
++ 0x01000000 0 0x00000000 0x1f600000 0 0x00010000 /* io space */
++ >;
++
++ pci0: pci at 0 {
++ reg = <0x2000 0 0 0 0>;
++ device_type = "pci";
++ #address-cells = <3>;
++ #size-cells = <2>;
++
++ status = "okay";
++
++ bus-range = <0 1>;
++ ranges;
++ };
++ };
++ };
++
++};
++
++&spi0 {
++ status = "okay";
++
++ flash at 0 {
++ compatible = "jedec,spi-nor";
++ reg = <0>;
++ spi-max-frequency = <10000000>;
++
++ partitions {
++ compatible = "fixed-partitions";
++ #address-cells = <1>;
++ #size-cells = <1>;
++
++ partition at 0 {
++ label = "Bootloader";
++ reg = <0x0 0x30000>;
++ read-only;
++ };
++
++ partition at 30000 {
++ label = "Config";
++ reg = <0x30000 0x10000>;
++ read-only;
++ };
++
++ factory: partition at 40000 {
++ label = "Factory";
++ reg = <0x40000 0x10000>;
++ read-only;
++ };
++
++ partition at 50000 {
++ compatible = "denx,uimage";
++ label = "Kernel";
++ reg = <0x50000 0x7b0000>;
++ };
++ };
++ };
++};
+diff --git a/arch/mips/boot/dts/ralink/wap300n.dts b/arch/mips/boot/dts/ralink/wap300n.dts
+new file mode 100644
+index 000000000000..9572a28bafa9
+--- /dev/null
++++ b/arch/mips/boot/dts/ralink/wap300n.dts
+@@ -0,0 +1,23 @@
++// SPDX-License-Identifier: GPL-2.0
++/dts-v1/;
++
++/include/ "rt6855.dtsi"
++
++/ {
++ compatible = "ralink,rt6855-soc";
++ model = "Linksys WAP300n";
++
++ memory at 0 {
++ device_type = "memory";
++ reg = <0x20000 0x3fe0000>;
++ };
++
++ chosen {
++ bootargs = "console=ttyS0,57600";
++ };
++
++ pci at 1fb80000 {
++ status = "okay";
++ };
++
++};
+diff --git a/arch/mips/include/asm/mach-ralink/ralink_regs.h b/arch/mips/include/asm/mach-ralink/ralink_regs.h
+index 9dbd9f0870c9..1cf8792d83a8 100644
+--- a/arch/mips/include/asm/mach-ralink/ralink_regs.h
++++ b/arch/mips/include/asm/mach-ralink/ralink_regs.h
+@@ -26,6 +26,7 @@ enum ralink_soc_type {
+ MT762X_SOC_MT7621AT,
+ MT762X_SOC_MT7628AN,
+ MT762X_SOC_MT7688,
++ RT6855_SOC,
+ };
+ extern enum ralink_soc_type ralink_soc;
+
+diff --git a/arch/mips/pci/Makefile b/arch/mips/pci/Makefile
+index d6de4cb2e31c..3a9be0a865f7 100644
+--- a/arch/mips/pci/Makefile
++++ b/arch/mips/pci/Makefile
+@@ -51,6 +51,7 @@ obj-$(CONFIG_PCI_LANTIQ) += pci-lantiq.o ops-lantiq.o
+ obj-$(CONFIG_SOC_MT7620) += pci-mt7620.o
+ obj-$(CONFIG_SOC_RT288X) += pci-rt2880.o
+ obj-$(CONFIG_SOC_RT3883) += pci-rt3883.o
++#obj-$(CONFIG_SOC_RT6855) += pci-rt3883.o
+ obj-$(CONFIG_TANBAC_TB0219) += fixup-tb0219.o
+ obj-$(CONFIG_TANBAC_TB0226) += fixup-tb0226.o
+ obj-$(CONFIG_TANBAC_TB0287) += fixup-tb0287.o
+diff --git a/arch/mips/pci/pci-legacy.c b/arch/mips/pci/pci-legacy.c
+index 39052de915f3..af4746f7ac3a 100644
+--- a/arch/mips/pci/pci-legacy.c
++++ b/arch/mips/pci/pci-legacy.c
+@@ -184,23 +184,30 @@ static DEFINE_MUTEX(pci_scan_mutex);
+ void register_pci_controller(struct pci_controller *hose)
+ {
+ struct resource *parent;
++ int err;
+
+ parent = hose->mem_resource->parent;
+ if (!parent)
+ parent = &iomem_resource;
+
+- if (request_resource(parent, hose->mem_resource) < 0)
++ if (request_resource(parent, hose->mem_resource) < 0) {
++ printk("%s(): line %d\n", __func__, __LINE__);
+ goto out;
++ }
+
+ parent = hose->io_resource->parent;
+ if (!parent)
+ parent = &ioport_resource;
+-
+- if (request_resource(parent, hose->io_resource) < 0) {
++/*
++ err = request_resource(parent, hose->io_resource);
++ if (err < 0) {
+ release_resource(hose->mem_resource);
++ printk("%s(): line %d err %d\n", __func__, __LINE__, err);
++ printk("%s(): IO %pR\n", __func__, hose->io_resource);
++ printk("%s(): MEM %pR\n", __func__, hose->mem_resource);
+ goto out;
+ }
+-
++*/
+ INIT_LIST_HEAD(&hose->list);
+ list_add_tail(&hose->list, &controllers);
+
+diff --git a/arch/mips/pci/pci-rt3883.c b/arch/mips/pci/pci-rt3883.c
+index 0ac6346026d0..300f3227719d 100644
+--- a/arch/mips/pci/pci-rt3883.c
++++ b/arch/mips/pci/pci-rt3883.c
+@@ -38,7 +38,7 @@
+ #define RT3883_PCI_REG_IOBASE 0x2c
+ #define RT3883_PCI_REG_ARBCTL 0x80
+
+-#define RT3883_PCI_REG_BASE(_x) (0x1000 + (_x) * 0x1000)
++#define RT3883_PCI_REG_BASE(_x) (0x2000 + (_x) * 0x1000)
+ #define RT3883_PCI_REG_BAR0SETUP(_x) (RT3883_PCI_REG_BASE((_x)) + 0x10)
+ #define RT3883_PCI_REG_IMBASEBAR0(_x) (RT3883_PCI_REG_BASE((_x)) + 0x18)
+ #define RT3883_PCI_REG_ID(_x) (RT3883_PCI_REG_BASE((_x)) + 0x30)
+@@ -92,8 +92,7 @@ static inline void rt3883_pci_w32(struct rt3883_pci_controller *rpc,
+ static inline u32 rt3883_pci_get_cfgaddr(unsigned int bus, unsigned int slot,
+ unsigned int func, unsigned int where)
+ {
+- return (bus << 16) | (slot << 11) | (func << 8) | (where & 0xfc) |
+- 0x80000000;
++ return (bus << 24) | (slot << 19) | (func << 16) | (where & 0xfc);
+ }
+
+ static u32 rt3883_pci_read_cfg32(struct rt3883_pci_controller *rpc,
+@@ -186,6 +185,7 @@ static struct irq_chip rt3883_pci_irq_chip = {
+ static int rt3883_pci_irq_map(struct irq_domain *d, unsigned int irq,
+ irq_hw_number_t hw)
+ {
++ printk("%s(irq=%d hwirq=%lu)\n", __func__, irq, hw);
+ irq_set_chip_and_handler(irq, &rt3883_pci_irq_chip, handle_level_irq);
+ irq_set_chip_data(irq, d->host_data);
+
+@@ -304,6 +304,7 @@ static struct pci_ops rt3883_pci_ops = {
+
+ static void rt3883_pci_preinit(struct rt3883_pci_controller *rpc, unsigned mode)
+ {
++#if 0
+ u32 syscfg1;
+ u32 rstctrl;
+ u32 clkcfg1;
+@@ -368,13 +369,36 @@ static void rt3883_pci_preinit(struct rt3883_pci_controller *rpc, unsigned mode)
+ * setup the device number of the P2P bridge
+ * and de-assert the reset line
+ */
++
+ t = (RT3883_P2P_BR_DEVNUM << RT3883_PCICFG_P2P_BR_DEVNUM_S);
+ rt3883_pci_w32(rpc, t, RT3883_PCI_REG_PCICFG);
+
+ /* flush write */
+ rt3883_pci_r32(rpc, RT3883_PCI_REG_PCICFG);
++#else
++ *((unsigned long *)(0xbfb00088)) &= ~(1<<22); // ok
++ msleep(1);
++ //assert PCIe RC1 reset signal
++ *((unsigned long *)(0xbfb00834)) |= ( 1<<27 ); // prevent boot
++ //disable reference clock of dev1
++ *((unsigned long *)(0xbfb00090)) &= ~( 1<<3 ); // ok
++ printk("0xbfb00834 = %lx\n", *((unsigned long *)(0xbfb00834)));
++ printk("0xbfb00088 = %lx\n", *((unsigned long *)(0xbfb00088)));
++
++#endif
+ msleep(500);
+
++
++ u32 t;
++ printk("BASE 0x%lx\n", (unsigned long)rpc->base);
++ printk("REG 0x%x\n", RT3883_PCI_REG_PCICFG);
++
++ t = rt3883_pci_r32(rpc, RT3883_PCI_REG_PCICFG);
++ t &= ~(1<<1);
++ rt3883_pci_w32(rpc, t, RT3883_PCI_REG_PCICFG);
++
++ msleep(500);
++#if 0
+ if (mode & RT3883_PCI_MODE_PCIE) {
+ msleep(500);
+
+@@ -403,6 +427,27 @@ static void rt3883_pci_preinit(struct rt3883_pci_controller *rpc, unsigned mode)
+
+ /* enable PCI arbiter */
+ rt3883_pci_w32(rpc, 0x79, RT3883_PCI_REG_ARBCTL);
++#else
++ if ((rt3883_pci_r32(rpc, RT3883_PCI_REG_STATUS(0)) & 0x1) == 0)
++ {
++ //assert PCIe RC0 reset signal
++ //*((unsigned long *)(0xbfb00834)) |= ( 1<<26 );
++ *((unsigned long *)(0xbfb00088)) &= ~( 1<<23 );
++ printk("PCIE0 no card, disable it\n");
++ }
++ if ((rt3883_pci_r32(rpc, RT3883_PCI_REG_STATUS(1)) & 0x1) == 0)
++ {
++ //PCI Control Register: Port1(bit22) disable
++ *((unsigned long *)(0xbfb00088)) &= ~(1<<22);
++ mdelay(1);
++ //assert PCIe RC1 reset signal
++ *((unsigned long *)(0xbfb00834)) |= ( 1<<27 );
++ mdelay(1);
++ //disable reference clock of dev1
++ *((unsigned long *)(0xbfb00090)) &= ~( 1<<3 );
++ printk("PCIE1 no card, disable it(RST&CLK)\n");
++ }
++#endif
+ }
+
+ static int rt3883_pci_probe(struct platform_device *pdev)
+@@ -456,7 +501,7 @@ static int rt3883_pci_probe(struct platform_device *pdev)
+ goto err_put_intc_node;
+ }
+
+- mode = RT3883_PCI_MODE_NONE;
++ mode = RT3883_PCI_MODE_PCIE;
+ for_each_available_child_of_node(rpc->pci_controller.of_node, child) {
+ int devfn;
+
+@@ -489,6 +534,7 @@ static int rt3883_pci_probe(struct platform_device *pdev)
+ (mode & RT3883_PCI_MODE_PCI) ? " PCI" : "",
+ (mode & RT3883_PCI_MODE_PCIE) ? " PCIe" : "");
+
++
+ rt3883_pci_preinit(rpc, mode);
+
+ rpc->pci_controller.pci_ops = &rt3883_pci_ops;
+@@ -499,6 +545,16 @@ static int rt3883_pci_probe(struct platform_device *pdev)
+ pci_load_of_ranges(&rpc->pci_controller,
+ rpc->pci_controller.of_node);
+
++ rpc->io_res.start = 0x1f600000;
++ rpc->io_res.end = 0x1f600000 + 0x0ffff;
++ rpc->io_res.flags = IORESOURCE_IO;
++
++ rpc->mem_res.start = 0x20000000;
++ rpc->mem_res.end = 0x20000000 + 0xfffffff;
++ rpc->mem_res.flags = IORESOURCE_MEM;
++
++ printk("PCI IO START 0x%x\n", rpc->io_res.start);
++
+ rt3883_pci_w32(rpc, rpc->mem_res.start, RT3883_PCI_REG_MEMBASE);
+ rt3883_pci_w32(rpc, rpc->io_res.start, RT3883_PCI_REG_IOBASE);
+
+@@ -506,33 +562,46 @@ static int rt3883_pci_probe(struct platform_device *pdev)
+ ioport_resource.end = rpc->io_res.end;
+
+ /* PCI */
+- rt3883_pci_w32(rpc, 0x03ff0000, RT3883_PCI_REG_BAR0SETUP(0));
++ rt3883_pci_w32(rpc, 0x7FFF0001, RT3883_PCI_REG_BAR0SETUP(0));
+ rt3883_pci_w32(rpc, RT3883_MEMORY_BASE, RT3883_PCI_REG_IMBASEBAR0(0));
+ rt3883_pci_w32(rpc, 0x08021814, RT3883_PCI_REG_ID(0));
+- rt3883_pci_w32(rpc, 0x00800001, RT3883_PCI_REG_CLASS(0));
++ rt3883_pci_w32(rpc, 0x06040001, RT3883_PCI_REG_CLASS(0));
+ rt3883_pci_w32(rpc, 0x28801814, RT3883_PCI_REG_SUBID(0));
+-
++#if 1
+ /* PCIe */
+- rt3883_pci_w32(rpc, 0x03ff0000, RT3883_PCI_REG_BAR0SETUP(1));
++ rt3883_pci_w32(rpc, 0x7FFF0001, RT3883_PCI_REG_BAR0SETUP(1));
+ rt3883_pci_w32(rpc, RT3883_MEMORY_BASE, RT3883_PCI_REG_IMBASEBAR0(1));
+ rt3883_pci_w32(rpc, 0x08021814, RT3883_PCI_REG_ID(1));
+ rt3883_pci_w32(rpc, 0x06040001, RT3883_PCI_REG_CLASS(1));
+ rt3883_pci_w32(rpc, 0x28801814, RT3883_PCI_REG_SUBID(1));
++#endif
++
++ val = rt3883_pci_r32(rpc, RT3883_PCI_REG_PCIENA);
++ rt3883_pci_w32(rpc, val | BIT(20) | BIT(21), RT3883_PCI_REG_PCIENA);
++// RALINK_PCI_PCIMSK_ADDR |= (1<<20); // enable pcie0 interrupt
++ //}
++ //if(pcie1_disable!=1){
++// RALINK_PCI_PCIMSK_ADDR |= (1<<21); // enable pcie1 interrupt
+
+ err = rt3883_pci_irq_init(dev, rpc);
+ if (err)
+ goto err_put_hb_node;
+-
++#if 0
+ /* PCIe */
+ val = rt3883_pci_read_cfg32(rpc, 0, 0x01, 0, PCI_COMMAND);
+ val |= PCI_COMMAND_IO | PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER;
+ rt3883_pci_write_cfg32(rpc, 0, 0x01, 0, PCI_COMMAND, val);
+-
++#endif
+ /* PCI */
++
+ val = rt3883_pci_read_cfg32(rpc, 0, 0x00, 0, PCI_COMMAND);
+ val |= PCI_COMMAND_IO | PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER;
+ rt3883_pci_write_cfg32(rpc, 0, 0x00, 0, PCI_COMMAND, val);
+
++ val = rt3883_pci_read_cfg32(rpc, 1, 0x00, 0, PCI_COMMAND);
++ val |= PCI_COMMAND_IO | PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER;
++ rt3883_pci_write_cfg32(rpc, 1, 0x00, 0, PCI_COMMAND, val);
++#if 0
+ if (mode == RT3883_PCI_MODE_PCIE) {
+ rt3883_pci_w32(rpc, 0x03ff0001, RT3883_PCI_REG_BAR0SETUP(0));
+ rt3883_pci_w32(rpc, 0x03ff0001, RT3883_PCI_REG_BAR0SETUP(1));
+@@ -547,7 +616,7 @@ static int rt3883_pci_probe(struct platform_device *pdev)
+ rt3883_pci_write_cfg32(rpc, 0, RT3883_P2P_BR_DEVNUM, 0,
+ PCI_IO_BASE, 0x00000101);
+ }
+-
++#endif
+ register_pci_controller(&rpc->pci_controller);
+
+ return 0;
+@@ -561,11 +630,13 @@ static int rt3883_pci_probe(struct platform_device *pdev)
+
+ int pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
+ {
++ printk("%s(slot %u pin %u)\n", __func__, slot, pin);
+ return of_irq_parse_and_map_pci(dev, slot, pin);
+ }
+
+ int pcibios_plat_dev_init(struct pci_dev *dev)
+ {
++ printk("%s()\n", __func__);
+ return 0;
+ }
+
+diff --git a/arch/mips/ralink/Kconfig b/arch/mips/ralink/Kconfig
+index 1434fa60f3db..0a24d0c705a0 100644
+--- a/arch/mips/ralink/Kconfig
++++ b/arch/mips/ralink/Kconfig
+@@ -16,7 +16,7 @@ config RALINK_ILL_ACC
+ config IRQ_INTC
+ bool
+ default y
+- depends on !SOC_MT7621
++ depends on !SOC_MT7621 && !SOC_RT6855
+
+ choice
+ prompt "Ralink SoC selection"
+@@ -36,6 +36,12 @@ choice
+ bool "RT3883"
+ select HAVE_PCI
+
++ config SOC_RT6855
++ bool "RT6855"
++ select HAVE_LEGACY_CLK
++ select HAVE_PCI
++ select MII
++
+ config SOC_MT7620
+ bool "MT7620/8"
+ select CPU_MIPSR2_IRQ_VI
+@@ -92,6 +98,11 @@ choice
+ depends on SOC_MT7620
+ select BUILTIN_DTB
+
++ config DTB_WAP300N
++ bool "WAP300N"
++ depends on SOC_RT6855
++ select BUILTIN_DTB
++
+ endchoice
+
+ endif
+diff --git a/arch/mips/ralink/Makefile b/arch/mips/ralink/Makefile
+index 26fabbdea1f1..1606929ff81f 100644
+--- a/arch/mips/ralink/Makefile
++++ b/arch/mips/ralink/Makefile
+@@ -7,7 +7,10 @@
+ obj-y := prom.o of.o reset.o
+
+ ifndef CONFIG_MIPS_GIC
+- obj-y += clk.o timer.o
++obj-y += clk.o
++ifndef CONFIG_SOC_RT6855
++ obj-y += timer.o
++endif
+ endif
+
+ obj-$(CONFIG_CLKEVT_RT3352) += cevt-rt3352.o
+@@ -22,6 +25,7 @@ obj-$(CONFIG_SOC_RT305X) += rt305x.o
+ obj-$(CONFIG_SOC_RT3883) += rt3883.o
+ obj-$(CONFIG_SOC_MT7620) += mt7620.o
+ obj-$(CONFIG_SOC_MT7621) += mt7621.o
++obj-$(CONFIG_SOC_RT6855) += rt6855.o irq-rt6855.o pci.o
+
+ obj-$(CONFIG_EARLY_PRINTK) += early_printk.o
+
+diff --git a/arch/mips/ralink/Platform b/arch/mips/ralink/Platform
+index 6095fcc334f4..89d897144ba1 100644
+--- a/arch/mips/ralink/Platform
++++ b/arch/mips/ralink/Platform
+@@ -22,6 +22,11 @@ cflags-$(CONFIG_SOC_RT305X) += -I$(srctree)/arch/mips/include/asm/mach-ralink/rt
+ load-$(CONFIG_SOC_RT3883) += 0xffffffff80000000
+ cflags-$(CONFIG_SOC_RT3883) += -I$(srctree)/arch/mips/include/asm/mach-ralink/rt3883
+
++# Ralink RT6855
++#
++load-$(CONFIG_SOC_RT6855) += 0xffffffff80020000
++cflags-$(CONFIG_SOC_RT6855) += $(call as-option,-Wa$(comma)-mno-fix-loongson3-llsc,)
++
+ #
+ # Ralink MT7620
+ #
+diff --git a/arch/mips/ralink/early_printk.c b/arch/mips/ralink/early_printk.c
+index eb4fac25eaf6..eb5f04809e8a 100644
+--- a/arch/mips/ralink/early_printk.c
++++ b/arch/mips/ralink/early_printk.c
+@@ -16,6 +16,9 @@
+ #elif defined(CONFIG_SOC_MT7621)
+ #define EARLY_UART_BASE 0x1E000c00
+ #define CHIPID_BASE 0x1E000004
++#elif defined(CONFIG_SOC_RT6855)
++#define EARLY_UART_BASE 0x1FBF0000
++#define CHIPID_BASE 0x1E000004
+ #else
+ #define EARLY_UART_BASE 0x10000c00
+ #define CHIPID_BASE 0x10000004
+@@ -74,7 +77,7 @@ void prom_putchar(char ch)
+ init_complete = 1;
+ }
+
+- if (IS_ENABLED(CONFIG_SOC_MT7621) || soc_is_mt7628()) {
++ if (IS_ENABLED(CONFIG_SOC_MT7621) || soc_is_mt7628() || IS_ENABLED(CONFIG_SOC_RT6855)) {
+ uart_w32((unsigned char)ch, UART_TX);
+ while ((uart_r32(UART_REG_LSR) & UART_LSR_THRE) == 0)
+ ;
+diff --git a/arch/mips/ralink/eureka_ep430.h b/arch/mips/ralink/eureka_ep430.h
+new file mode 100755
+index 000000000000..8eac5e5016a3
+--- /dev/null
++++ b/arch/mips/ralink/eureka_ep430.h
+@@ -0,0 +1,186 @@
++/**************************************************************************
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of the GNU General Public License as published by the
++ * Free Software Foundation; either version 2 of the License, or (at your
++ * option) any later version.
++ *
++ * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
++ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
++ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
++ * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
++ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
++ * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
++ * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
++ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
++ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
++ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
++ *
++ * You should have received a copy of the GNU General Public License along
++ * with this program; if not, write to the Free Software Foundation, Inc.,
++ * 675 Mass Ave, Cambridge, MA 02139, USA.
++ *
++ *
++ **************************************************************************
++ */
++
++#define CONFIG_RALINK_RT6855A
++#ifndef _EUREKA_EP430_H
++#define _EUREKA_EP430_H
++
++
++#include <asm/addrspace.h> /* for KSEG1ADDR() */
++#include <asm/byteorder.h> /* for cpu_to_le32() */
++#include "rt_mmap.h"
++
++
++/*
++ * Because of an error/peculiarity in the Galileo chip, we need to swap the
++ * bytes when running bigendian.
++ */
++
++#define MV_WRITE(ofs, data) \
++ *(volatile u32 *)(RALINK_PCI_BASE+(ofs)) = cpu_to_le32(data)
++#define MV_READ(ofs, data) \
++ *(data) = le32_to_cpu(*(volatile u32 *)(RALINK_PCI_BASE+(ofs)))
++#define MV_READ_DATA(ofs) \
++ le32_to_cpu(*(volatile u32 *)(RALINK_PCI_BASE+(ofs)))
++
++#define MV_WRITE_16(ofs, data) \
++ *(volatile u16 *)(RALINK_PCI_BASE+(ofs)) = cpu_to_le16(data)
++#define MV_READ_16(ofs, data) \
++ *(data) = le16_to_cpu(*(volatile u16 *)(RALINK_PCI_BASE+(ofs)))
++
++#define MV_WRITE_8(ofs, data) \
++ *(volatile u8 *)(RALINK_PCI_BASE+(ofs)) = data
++#define MV_READ_8(ofs, data) \
++ *(data) = *(volatile u8 *)(RALINK_PCI_BASE+(ofs))
++
++#define MV_SET_REG_BITS(ofs,bits) \
++ (*((volatile u32 *)(RALINK_PCI_BASE+(ofs)))) |= ((u32)cpu_to_le32(bits))
++#define MV_RESET_REG_BITS(ofs,bits) \
++ (*((volatile u32 *)(RALINK_PCI_BASE+(ofs)))) &= ~((u32)cpu_to_le32(bits))
++
++#define RALINK_PCI_CONFIG_ADDR 0x20
++#define RALINK_PCI_CONFIG_DATA_VIRTUAL_REG 0x24
++
++#if defined(CONFIG_RALINK_RT2880) || defined(CONFIG_RALINK_RT2883)
++#define RALINK_PCI_PCICFG_ADDR *(volatile u32 *)(RALINK_PCI_BASE + 0x0000)
++#define RALINK_PCI_PCIRAW_ADDR *(volatile u32 *)(RALINK_PCI_BASE + 0x0004)
++#define RALINK_PCI_PCIINT_ADDR *(volatile u32 *)(RALINK_PCI_BASE + 0x0008)
++#define RALINK_PCI_PCIMSK_ADDR *(volatile u32 *)(RALINK_PCI_BASE + 0x000C)
++#define RALINK_PCI_BAR0SETUP_ADDR *(volatile u32 *)(RALINK_PCI_BASE + 0x0010)
++#define RALINK_PCI_IMBASEBAR0_ADDR *(volatile u32 *)(RALINK_PCI_BASE + 0x0018)
++#define RALINK_PCI_IMBASEBAR1_ADDR *(volatile u32 *)(RALINK_PCI_BASE + 0x001C)
++#define RALINK_PCI_MEMBASE *(volatile u32 *)(RALINK_PCI_BASE + 0x0028)
++#define RALINK_PCI_IOBASE *(volatile u32 *)(RALINK_PCI_BASE + 0x002C)
++#define RALINK_PCI_ID *(volatile u32 *)(RALINK_PCI_BASE + 0x0030)
++#define RALINK_PCI_CLASS *(volatile u32 *)(RALINK_PCI_BASE + 0x0034)
++#define RALINK_PCI_SUBID *(volatile u32 *)(RALINK_PCI_BASE + 0x0038)
++#define RALINK_PCI_ARBCTL *(volatile u32 *)(RALINK_PCI_BASE + 0x0080)
++#define RALINK_PCI_STATUS *(volatile u32 *)(RALINK_PCI_BASE + 0x0050)
++
++#elif defined(CONFIG_RALINK_RT3883)
++
++#define RALINK_PCI_PCICFG_ADDR *(volatile u32 *)(RALINK_PCI_BASE + 0x0000)
++#define RALINK_PCI_PCIRAW_ADDR *(volatile u32 *)(RALINK_PCI_BASE + 0x0004)
++#define RALINK_PCI_PCIINT_ADDR *(volatile u32 *)(RALINK_PCI_BASE + 0x0008)
++#define RALINK_PCI_PCIMSK_ADDR *(volatile u32 *)(RALINK_PCI_BASE + 0x000C)
++#define RALINK_PCI_IMBASEBAR1_ADDR *(volatile u32 *)(RALINK_PCI_BASE + 0x001C)
++#define RALINK_PCI_MEMBASE *(volatile u32 *)(RALINK_PCI_BASE + 0x0028)
++#define RALINK_PCI_IOBASE *(volatile u32 *)(RALINK_PCI_BASE + 0x002C)
++#define RALINK_PCI_ARBCTL *(volatile u32 *)(RALINK_PCI_BASE + 0x0080)
++
++/*
++PCI0 --> PCI
++PCI1 --> PCIe
++*/
++#define RT3883_PCI_OFFSET 0x1000
++#define RT3883_PCIE_OFFSET 0x2000
++
++#define RALINK_PCI0_BAR0SETUP_ADDR *(volatile u32 *)(RALINK_PCI_BASE + RT3883_PCI_OFFSET + 0x0010)
++#define RALINK_PCI0_IMBASEBAR0_ADDR *(volatile u32 *)(RALINK_PCI_BASE + RT3883_PCI_OFFSET + 0x0018)
++#define RALINK_PCI0_ID *(volatile u32 *)(RALINK_PCI_BASE + RT3883_PCI_OFFSET + 0x0030)
++#define RALINK_PCI0_CLASS *(volatile u32 *)(RALINK_PCI_BASE + RT3883_PCI_OFFSET + 0x0034)
++#define RALINK_PCI0_SUBID *(volatile u32 *)(RALINK_PCI_BASE + RT3883_PCI_OFFSET + 0x0038)
++
++#define RALINK_PCI1_BAR0SETUP_ADDR *(volatile u32 *)(RALINK_PCI_BASE + RT3883_PCIE_OFFSET + 0x0010)
++#define RALINK_PCI1_IMBASEBAR0_ADDR *(volatile u32 *)(RALINK_PCI_BASE + RT3883_PCIE_OFFSET + 0x0018)
++#define RALINK_PCI1_ID *(volatile u32 *)(RALINK_PCI_BASE + RT3883_PCIE_OFFSET + 0x0030)
++#define RALINK_PCI1_CLASS *(volatile u32 *)(RALINK_PCI_BASE + RT3883_PCIE_OFFSET + 0x0034)
++#define RALINK_PCI1_SUBID *(volatile u32 *)(RALINK_PCI_BASE + RT3883_PCIE_OFFSET + 0x0038)
++#define RALINK_PCI1_STATUS *(volatile u32 *)(RALINK_PCI_BASE + RT3883_PCIE_OFFSET + 0x0050)
++
++#elif defined(CONFIG_RALINK_RT6855)
++
++#define RALINK_PCI_PCICFG_ADDR *(volatile u32 *)(RALINK_PCI_BASE + 0x0000)
++#define RALINK_PCI_PCIRAW_ADDR *(volatile u32 *)(RALINK_PCI_BASE + 0x0004)
++#define RALINK_PCI_PCIINT_ADDR *(volatile u32 *)(RALINK_PCI_BASE + 0x0008)
++#define RALINK_PCI_PCIMSK_ADDR *(volatile u32 *)(RALINK_PCI_BASE + 0x000C)
++#define RALINK_PCI_IMBASEBAR1_ADDR *(volatile u32 *)(RALINK_PCI_BASE + 0x001C)
++#define RALINK_PCI_MEMBASE *(volatile u32 *)(RALINK_PCI_BASE + 0x0028)
++#define RALINK_PCI_IOBASE *(volatile u32 *)(RALINK_PCI_BASE + 0x002C)
++#define RALINK_PCI_ARBCTL *(volatile u32 *)(RALINK_PCI_BASE + 0x0080)
++
++/*
++PCI0 --> PCIe 0
++PCI1 --> PCIe 1
++*/
++#define RT6855_PCIE0_OFFSET 0x2000
++#define RT6855_PCIE1_OFFSET 0x3000
++
++#define RALINK_PCI0_BAR0SETUP_ADDR *(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE0_OFFSET + 0x0010)
++#define RALINK_PCI0_IMBASEBAR0_ADDR *(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE0_OFFSET + 0x0018)
++#define RALINK_PCI0_ID *(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE0_OFFSET + 0x0030)
++#define RALINK_PCI0_CLASS *(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE0_OFFSET + 0x0034)
++#define RALINK_PCI0_SUBID *(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE0_OFFSET + 0x0038)
++#define RALINK_PCI0_STATUS *(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE0_OFFSET + 0x0050)
++
++#define RALINK_PCI1_BAR0SETUP_ADDR *(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE1_OFFSET + 0x0010)
++#define RALINK_PCI1_IMBASEBAR0_ADDR *(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE1_OFFSET + 0x0018)
++#define RALINK_PCI1_ID *(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE1_OFFSET + 0x0030)
++#define RALINK_PCI1_CLASS *(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE1_OFFSET + 0x0034)
++#define RALINK_PCI1_SUBID *(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE1_OFFSET + 0x0038)
++#define RALINK_PCI1_STATUS *(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE1_OFFSET + 0x0050)
++
++#elif defined(CONFIG_RALINK_RT6855A)
++
++#define RALINK_PCI_PCICFG_ADDR *(volatile u32 *)(RALINK_PCI_BASE + 0x0000)
++#define RALINK_PCI_PCIRAW_ADDR *(volatile u32 *)(RALINK_PCI_BASE + 0x0004)
++#define RALINK_PCI_PCIINT_ADDR *(volatile u32 *)(RALINK_PCI_BASE + 0x0008)
++#define RALINK_PCI_PCIMSK_ADDR *(volatile u32 *)(RALINK_PCI_BASE + 0x000C)
++#define RALINK_PCI_IMBASEBAR1_ADDR *(volatile u32 *)(RALINK_PCI_BASE + 0x001C)
++#define RALINK_PCI_MEMBASE *(volatile u32 *)(RALINK_PCI_BASE + 0x0028)
++#define RALINK_PCI_IOBASE *(volatile u32 *)(RALINK_PCI_BASE + 0x002C)
++#define RALINK_PCI_ARBCTL *(volatile u32 *)(RALINK_PCI_BASE + 0x0080)
++
++/*
++PCI0 --> PCIe 0
++PCI1 --> PCIe 1
++*/
++#define RT6855_PCIE0_OFFSET 0x2000
++#define RT6855_PCIE1_OFFSET 0x3000
++
++#define RALINK_PCI0_BAR0SETUP_ADDR *(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE0_OFFSET + 0x0010)
++#define RALINK_PCI0_IMBASEBAR0_ADDR *(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE0_OFFSET + 0x0018)
++#define RALINK_PCI0_ID *(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE0_OFFSET + 0x0030)
++#define RALINK_PCI0_CLASS *(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE0_OFFSET + 0x0034)
++#define RALINK_PCI0_SUBID *(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE0_OFFSET + 0x0038)
++#define RALINK_PCI0_STATUS *(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE0_OFFSET + 0x0050)
++#define RALINK_PCI0_ECRC *(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE0_OFFSET + 0x0064)
++
++
++#define RALINK_PCI1_BAR0SETUP_ADDR *(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE1_OFFSET + 0x0010)
++#define RALINK_PCI1_IMBASEBAR0_ADDR *(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE1_OFFSET + 0x0018)
++#define RALINK_PCI1_ID *(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE1_OFFSET + 0x0030)
++#define RALINK_PCI1_CLASS *(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE1_OFFSET + 0x0034)
++#define RALINK_PCI1_SUBID *(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE1_OFFSET + 0x0038)
++#define RALINK_PCI1_STATUS *(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE1_OFFSET + 0x0050)
++#define RALINK_PCI1_ECRC *(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE1_OFFSET + 0x0064)
++
++#elif defined(CONFIG_RALINK_RT3052) || defined(CONFIG_RALINK_RT3352) || defined(CONFIG_RALINK_RT5350)
++#else
++#error "undefined in PCI"
++#endif
++
++#endif
+diff --git a/arch/mips/ralink/irq-rt6855.c b/arch/mips/ralink/irq-rt6855.c
+new file mode 100644
+index 000000000000..f4174d66f4f4
+--- /dev/null
++++ b/arch/mips/ralink/irq-rt6855.c
+@@ -0,0 +1,171 @@
++// SPDX-License-Identifier: GPL-2.0-only
++/*
++ *
++ * Copyright (C) 2009 Gabor Juhos <juhosg at openwrt.org>
++ * Copyright (C) 2013 John Crispin <john at phrozen.org>
++ */
++
++#include <linux/io.h>
++#include <linux/bitops.h>
++#include <linux/of_platform.h>
++#include <linux/of_address.h>
++#include <linux/of_irq.h>
++#include <linux/irqdomain.h>
++#include <linux/interrupt.h>
++
++#include <asm/irq_cpu.h>
++#include <ioremap.h>
++#include <asm/mipsregs.h>
++
++#include "common.h"
++
++/* we have a cascade of 8 irqs */
++#define RALINK_INTC_IRQ_BASE 8
++
++/* we have 32 SoC irqs */
++#define RALINK_INTC_IRQ_COUNT 32
++
++#define RALINK_SOC_IRQ_TIMER 30
++
++enum rt_intc_regs_enum {
++ INTC_REG_MASK = 0,
++ INTC_REG_PRIO,
++};
++
++static u32 rt_intc_regs[] = {
++ [INTC_REG_MASK] = 0x04,
++ [INTC_REG_PRIO] = 0x10,
++};
++
++static DEFINE_SPINLOCK(rt6855_irq_lock);
++
++static void __iomem *rt_intc_membase;
++
++static inline void rt_intc_w32(u32 val, unsigned reg)
++{
++ __raw_writel(val, rt_intc_membase + rt_intc_regs[reg]);
++}
++
++static inline void rt_intc_prio_w8(u32 val, unsigned prio)
++{
++ __raw_writeb(val, rt_intc_membase + rt_intc_regs[INTC_REG_PRIO] + prio);
++}
++
++static inline u32 rt_intc_r32(unsigned reg)
++{
++ return __raw_readl(rt_intc_membase + rt_intc_regs[reg]);
++}
++
++static void ralink_intc_irq_unmask(struct irq_data *d)
++{
++ unsigned long flags;
++ u32 mask;
++
++ spin_lock_irqsave(&rt6855_irq_lock, flags);
++
++ mask = rt_intc_r32(INTC_REG_MASK);
++ mask |= BIT(d->hwirq);
++ rt_intc_w32(mask, INTC_REG_MASK);
++
++ spin_unlock_irqrestore(&rt6855_irq_lock, flags);
++}
++
++static void ralink_intc_irq_mask(struct irq_data *d)
++{
++ unsigned long flags;
++ u32 mask;
++
++ spin_lock_irqsave(&rt6855_irq_lock, flags);
++
++ mask = rt_intc_r32(INTC_REG_MASK);
++ mask &= ~BIT(d->hwirq);
++ rt_intc_w32(mask, INTC_REG_MASK);
++
++ spin_unlock_irqrestore(&rt6855_irq_lock, flags);
++}
++
++static struct irq_chip ralink_intc_irq_chip = {
++ .name = "INTC",
++ .irq_ack = ralink_intc_irq_mask,
++ .irq_mask = ralink_intc_irq_mask,
++ .irq_mask_ack = ralink_intc_irq_mask,
++ .irq_unmask = ralink_intc_irq_unmask,
++ .irq_eoi = ralink_intc_irq_unmask,
++};
++
++unsigned int get_c0_compare_int(void)
++{
++ return RALINK_INTC_IRQ_BASE + RALINK_SOC_IRQ_TIMER;
++}
++
++asmlinkage void plat_irq_dispatch(void)
++{
++ unsigned long pending;
++
++ pending = (read_c0_status() & read_c0_cause() & ST0_IM) >> 10;
++
++ do_IRQ(pending + RALINK_INTC_IRQ_BASE - 1);
++}
++
++static int intc_map(struct irq_domain *d, unsigned int irq, irq_hw_number_t hw)
++{
++ irq_set_chip_and_handler(irq, &ralink_intc_irq_chip, handle_level_irq);
++
++ return 0;
++}
++
++static const struct irq_domain_ops irq_domain_ops = {
++ .xlate = irq_domain_xlate_onecell,
++ .map = intc_map,
++};
++
++static int __init intc_of_init(struct device_node *node,
++ struct device_node *parent)
++{
++ struct resource res;
++ struct irq_domain *domain;
++
++ if (!of_property_read_u32_array(node, "ralink,intc-registers",
++ rt_intc_regs, 2))
++ pr_info("intc: using register map from devicetree\n");
++
++ if (of_address_to_resource(node, 0, &res))
++ panic("Failed to get intc memory range");
++
++ if (!request_mem_region(res.start, resource_size(&res),
++ res.name))
++ pr_err("Failed to request intc memory");
++
++ rt_intc_membase = ioremap(res.start,
++ resource_size(&res));
++ if (!rt_intc_membase)
++ panic("Failed to remap intc memory");
++
++ rt_intc_prio_w8(RALINK_SOC_IRQ_TIMER, 4);
++ rt_intc_prio_w8(24, 3);
++ rt_intc_prio_w8(21, 2);
++ rt_intc_prio_w8(15, 1);
++
++ clear_c0_status(ST0_IM);
++ clear_c0_cause(CAUSEF_IP);
++
++ domain = irq_domain_add_legacy(node, RALINK_INTC_IRQ_COUNT,
++ RALINK_INTC_IRQ_BASE, 0, &irq_domain_ops, NULL);
++ if (!domain)
++ panic("Failed to add irqdomain");
++
++ set_c0_status(ST0_IM);
++
++ return 0;
++}
++
++static struct of_device_id __initdata of_irq_ids[] = {
++ { .compatible = "mti,cpu-interrupt-controller", .data = mips_cpu_irq_of_init },
++ { .compatible = "ralink,rt6855-intc", .data = intc_of_init },
++ {},
++};
++
++void __init arch_init_irq(void)
++{
++ of_irq_init(of_irq_ids);
++}
+diff --git a/arch/mips/ralink/pci.c b/arch/mips/ralink/pci.c
+new file mode 100644
+index 000000000000..ba60b9ad77ca
+--- /dev/null
++++ b/arch/mips/ralink/pci.c
+@@ -0,0 +1,1067 @@
++/**************************************************************************
++ *
++ * BRIEF MODULE DESCRIPTION
++ * PCI init for Ralink solution
++ *
++ * Copyright 2007 Ralink Inc. (bruce_chang at ralinktech.com.tw)
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of the GNU General Public License as published by the
++ * Free Software Foundation; either version 2 of the License, or (at your
++ * option) any later version.
++ *
++ * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
++ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
++ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
++ * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
++ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
++ * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
++ * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
++ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
++ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
++ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
++ *
++ * You should have received a copy of the GNU General Public License along
++ * with this program; if not, write to the Free Software Foundation, Inc.,
++ * 675 Mass Ave, Cambridge, MA 02139, USA.
++ *
++ *
++ **************************************************************************
++ * May 2007 Bruce Chang
++ * Initial Release
++ *
++ * May 2009 Bruce Chang
++ * support RT2880/RT3883 PCIe
++ *
++ * Feb 2011 Bruce Chang
++ * support RT6855 PCI and PCIe architecture
++ *
++ * Sep 2011 Bruce Chang
++ * support RT6855A PCIe architecture
++ *
++ **************************************************************************
++ */
++
++
++#define CONFIG_RT6855A_PCIE_PORT01_ENABLE
++#include <linux/types.h>
++#include <linux/pci.h>
++#include <linux/kernel.h>
++#include <linux/slab.h>
++#include <linux/version.h>
++#include <asm/pci.h>
++#include <asm/io.h>
++#include "eureka_ep430.h"
++#include <linux/init.h>
++#include <linux/mod_devicetable.h>
++#include <linux/delay.h>
++//#include <asm/rt2880/surfboardint.h>
++
++#define RALINK_INT_PCIE0 32 /* PCIE0 */
++#define RALINK_INT_PCIE1 31 /* PCIE1 */
++
++
++
++#ifdef CONFIG_PCI
++
++/*
++ * These functions and structures provide the BIOS scan and mapping of the PCI
++ * devices.
++ */
++
++#define RALINK_PCI_MM_MAP_BASE 0x20000000
++
++#if defined(CONFIG_RALINK_RT2883) || defined(CONFIG_RALINK_RT3883) || defined(CONFIG_RALINK_RT6855)
++#define RALINK_PCI_IO_MAP_BASE 0x10160000
++#elif defined(CONFIG_RALINK_RT6855A)
++#define RALINK_PCI_IO_MAP_BASE 0x1f600000
++#else
++#define RALINK_PCI_IO_MAP_BASE 0x00460000
++#endif
++
++#define RALINK_SYSTEM_CONTROL_BASE 0xb0000000
++#define RALINK_SYSCFG1 *(unsigned long *)(RALINK_SYSTEM_CONTROL_BASE + 0x14)
++#define RALINK_CLKCFG1 *(unsigned long *)(RALINK_SYSTEM_CONTROL_BASE + 0x30)
++#define RALINK_RSTCTRL *(unsigned long *)(RALINK_SYSTEM_CONTROL_BASE + 0x34)
++#define RALINK_GPIOMODE *(unsigned long *)(RALINK_SYSTEM_CONTROL_BASE + 0x60)
++#define RALINK_PCIE_CLK_GEN *(unsigned long *)(RALINK_SYSTEM_CONTROL_BASE + 0x7c)
++#define RALINK_PCIE_CLK_GEN1 *(unsigned long *)(RALINK_SYSTEM_CONTROL_BASE + 0x80)
++//RALINK_SYSCFG1 bit
++#define RALINK_PCI_HOST_MODE_EN (1<<7)
++#define RALINK_PCIE_RC_MODE_EN (1<<8)
++//RALINK_RSTCTRL bit
++#define RALINK_PCIE_RST (1<<23)
++#define RALINK_PCI_RST (1<<24)
++//RALINK_CLKCFG1 bit
++#define RALINK_PCI_CLK_EN (1<<19)
++#define RALINK_PCIE_CLK_EN (1<<21)
++//RALINK_GPIOMODE bit
++#define PCI_SLOTx2 (1<<11)
++#define PCI_SLOTx1 (2<<11)
++
++
++#if defined(CONFIG_RALINK_RT2883) || defined(CONFIG_RALINK_RT3883) || defined(CONFIG_RALINK_RT6855) || defined(CONFIG_RALINK_RT6855A)
++#define MEMORY_BASE 0x0
++#else
++#define MEMORY_BASE 0x08000000
++#endif
++
++#if defined(CONFIG_RALINK_RT6855) || defined(CONFIG_RALINK_RT6855A)
++ //pcie_disable = 0 mean there is a card on this slot
++ //pcie_disable = 1 mean there is no card on this slot
++ int pcie0_disable =0;
++ int pcie1_disable =0;
++#endif
++//extern pci_probe_only;
++
++void __inline__ read_config(unsigned long bus, unsigned long dev, unsigned long func, unsigned long reg, unsigned long *val);
++void __inline__ write_config(unsigned long bus, unsigned long dev, unsigned long func, unsigned long reg, unsigned long val);
++
++#if 1
++
++#define PCI_ACCESS_READ_1 0
++#define PCI_ACCESS_READ_2 1
++#define PCI_ACCESS_READ_4 2
++#define PCI_ACCESS_WRITE_1 3
++#define PCI_ACCESS_WRITE_2 4
++#define PCI_ACCESS_WRITE_4 5
++
++static int config_access(unsigned char access_type, struct pci_bus *bus,
++ unsigned int devfn, unsigned char where,
++ u32 * data)
++{
++ unsigned int slot = PCI_SLOT(devfn);
++ u8 func = PCI_FUNC(devfn);
++ uint32_t address_reg, data_reg;
++ unsigned int address;
++
++ address_reg = RALINK_PCI_CONFIG_ADDR;
++ data_reg = RALINK_PCI_CONFIG_DATA_VIRTUAL_REG;
++
++ /* Setup address */
++#if defined(CONFIG_RALINK_RT2883)
++ address = (bus->number << 24) | (slot << 19) | (func << 16) | (where & 0xfc)| 0x1;
++#elif defined (CONFIG_RALINK_RT3883)
++ address = (bus->number << 16) | (slot << 11) | (func << 8) | (where & 0xfc) | 0x80000000;
++#elif defined (CONFIG_RALINK_RT6855)
++ address = (bus->number << 16) | (slot << 11) | (func << 8) | (where & 0xfc) | 0x80000000;
++#elif defined(CONFIG_RALINK_RT6855A)
++ address = (bus->number << 24) | (slot << 19) | (func << 16) | (where & 0xfc);
++#else
++ address = (bus->number << 16) | (slot << 11) | (func << 8) | (where& 0xfc) | 0x80000000;
++#endif
++ /* start the configuration cycle */
++ MV_WRITE(address_reg, address);
++
++ switch(access_type) {
++ case PCI_ACCESS_WRITE_1:
++ MV_WRITE_8(data_reg+(where&0x3), *data);
++ break;
++ case PCI_ACCESS_WRITE_2:
++ MV_WRITE_16(data_reg+(where&0x3), *data);
++ break;
++ case PCI_ACCESS_WRITE_4:
++ MV_WRITE(data_reg, *data);
++ break;
++ case PCI_ACCESS_READ_1:
++ MV_READ_8( data_reg+(where&0x3), data);
++ break;
++ case PCI_ACCESS_READ_2:
++ MV_READ_16(data_reg+(where&0x3), data);
++ break;
++ case PCI_ACCESS_READ_4:
++ MV_READ(data_reg, data);
++ break;
++ default:
++ printk("no specify access type\n");
++ break;
++ }
++ //if (bus->number==1&&where==0x30){
++ //printk("_%x->[%x][%x][%x][%x]=%x\n",access_type,bus->number, slot, func, where, *data);
++ //}
++ return 0;
++}
++
++
++
++static int read_config_byte(struct pci_bus *bus, unsigned int devfn,
++ int where, u8 * val)
++{
++ //u32 data;
++ int ret;
++
++ ret = config_access(PCI_ACCESS_READ_1, bus, devfn, (unsigned char)where, (u32 *)val);
++ //*val = (data >> ((where & 3) << 3)) & 0xff;
++ return ret;
++}
++
++static int read_config_word(struct pci_bus *bus, unsigned int devfn,
++ int where, u16 * val)
++{
++ //u32 data;
++ int ret;
++
++ ret = config_access(PCI_ACCESS_READ_2, bus, devfn, (unsigned char)where, (u32 *)val);
++ //*val = (data >> ((where & 3) << 3)) & 0xffff;
++ return ret;
++}
++
++static int read_config_dword(struct pci_bus *bus, unsigned int devfn,
++ int where, u32 * val)
++{
++ int ret;
++
++ ret = config_access(PCI_ACCESS_READ_4, bus, devfn, (unsigned char)where, (u32 *)val);
++ return ret;
++}
++static int
++write_config_byte(struct pci_bus *bus, unsigned int devfn, int where,
++ u8 val)
++{
++ if (config_access(PCI_ACCESS_WRITE_1, bus, devfn, (unsigned char)where, (u32 *)&val))
++ return -1;
++
++ return PCIBIOS_SUCCESSFUL;
++}
++
++static int
++write_config_word(struct pci_bus *bus, unsigned int devfn, int where,
++ u16 val)
++{
++ if (config_access(PCI_ACCESS_WRITE_2, bus, devfn, where, (u32 *)&val))
++ return -1;
++
++
++ return PCIBIOS_SUCCESSFUL;
++}
++
++static int
++write_config_dword(struct pci_bus *bus, unsigned int devfn, int where,
++ u32 val)
++{
++ if (config_access(PCI_ACCESS_WRITE_4, bus, devfn, where, &val))
++ return -1;
++
++ return PCIBIOS_SUCCESSFUL;
++}
++#else
++#define PCI_ACCESS_READ 0
++#define PCI_ACCESS_WRITE 1
++
++static int config_access(unsigned char access_type, struct pci_bus *bus,
++ unsigned int devfn, unsigned char where,
++ u32 * data)
++{
++ unsigned int slot = PCI_SLOT(devfn);
++ u8 func = PCI_FUNC(devfn);
++ uint32_t address_reg, data_reg;
++ unsigned int address;
++
++ address_reg = RALINK_PCI_CONFIG_ADDR;
++ data_reg = RALINK_PCI_CONFIG_DATA_VIRTUAL_REG;
++
++ /* Setup address */
++#ifdef CONFIG_RALINK_RT2883
++ address = (bus->number << 24) | (slot << 19) | (func << 16) | (where & 0xfc)| 0x1;
++#elif CONFIG_RALINK_RT3883
++ address = (bus->number << 16) | (slot << 11) | (func << 8) | (where & 0xfc) | 0x80000000;
++#elif defined (CONFIG_RALINK_RT6855)
++ address = (bus->number << 16) | (slot << 11) | (func << 8) | (where & 0xfc) | 0x80000000;
++#elif defined(CONFIG_RALINK_RT6855A)
++ address = (bus->number << 24) | (slot << 19) | (func << 16) | (where & 0xfc);
++#else
++ address = (bus->number << 16) | (slot << 11) | (func << 8) | (where& 0xfc) | 0x80000000;
++#endif
++ /* start the configuration cycle */
++ MV_WRITE(address_reg, address);
++
++ if (access_type == PCI_ACCESS_WRITE){
++ MV_WRITE(data_reg, *data);
++ }else{
++ MV_READ(data_reg, data);
++ }
++ //printk("-%x->[%x][%x][%x][%x]=%x\n",access_type,bus->number, slot, func, where, *data);
++ return 0;
++}
++
++
++
++static int read_config_byte(struct pci_bus *bus, unsigned int devfn,
++ int where, u8 * val)
++{
++ u32 data;
++ int ret;
++
++ ret = config_access(PCI_ACCESS_READ, bus, devfn, where, &data);
++ *val = (data >> ((where & 3) << 3)) & 0xff;
++ return ret;
++}
++
++static int read_config_word(struct pci_bus *bus, unsigned int devfn,
++ int where, u16 * val)
++{
++ u32 data;
++ int ret;
++
++ ret = config_access(PCI_ACCESS_READ, bus, devfn, where, &data);
++ *val = (data >> ((where & 3) << 3)) & 0xffff;
++ return ret;
++}
++
++static int read_config_dword(struct pci_bus *bus, unsigned int devfn,
++ int where, u32 * val)
++{
++ int ret;
++
++ ret = config_access(PCI_ACCESS_READ, bus, devfn, where, val);
++ return ret;
++}
++static int
++write_config_byte(struct pci_bus *bus, unsigned int devfn, int where,
++ u8 val)
++{
++ u32 data = 0;
++
++ if (config_access(PCI_ACCESS_READ, bus, devfn, where, &data))
++ return -1;
++
++ data = (data & ~(0xff << ((where & 3) << 3))) |
++ (val << ((where & 3) << 3));
++
++ if (config_access(PCI_ACCESS_WRITE, bus, devfn, where, &data))
++ return -1;
++
++ return PCIBIOS_SUCCESSFUL;
++}
++
++static int
++write_config_word(struct pci_bus *bus, unsigned int devfn, int where,
++ u16 val)
++{
++ u32 data = 0;
++
++ if (config_access(PCI_ACCESS_READ, bus, devfn, where, &data))
++ return -1;
++
++ data = (data & ~(0xffff << ((where & 3) << 3))) |
++ (val << ((where & 3) << 3));
++
++ if (config_access(PCI_ACCESS_WRITE, bus, devfn, where, &data))
++ return -1;
++
++
++ return PCIBIOS_SUCCESSFUL;
++}
++
++static int
++write_config_dword(struct pci_bus *bus, unsigned int devfn, int where,
++ u32 val)
++{
++ if (config_access(PCI_ACCESS_WRITE, bus, devfn, where, &val))
++ return -1;
++
++ return PCIBIOS_SUCCESSFUL;
++}
++#endif
++
++static int pci_config_read(struct pci_bus *bus, unsigned int devfn,
++ int where, int size, u32 * val)
++{
++ switch (size) {
++ case 1:
++ return read_config_byte(bus, devfn, where, (u8 *) val);
++ case 2:
++ return read_config_word(bus, devfn, where, (u16 *) val);
++ default:
++ return read_config_dword(bus, devfn, where, val);
++ }
++}
++
++static int pci_config_write(struct pci_bus *bus, unsigned int devfn,
++ int where, int size, u32 val)
++{
++ switch (size) {
++ case 1:
++ return write_config_byte(bus, devfn, where, (u8) val);
++ case 2:
++ return write_config_word(bus, devfn, where, (u16) val);
++ default:
++ return write_config_dword(bus, devfn, where, val);
++ }
++}
++
++
++/*
++ * General-purpose PCI functions.
++ */
++
++struct pci_ops rt2880_pci_ops= {
++ .read = pci_config_read,
++ .write = pci_config_write,
++};
++
++static struct resource rt2880_res_pci_mem1 = {
++ .name = "PCI MEM1",
++ .start = RALINK_PCI_MM_MAP_BASE,
++ .end = (u32)((RALINK_PCI_MM_MAP_BASE + (unsigned char *)0x0fffffff)),
++ .flags = IORESOURCE_MEM,
++};
++static struct resource rt2880_res_pci_io1 = {
++ .name = "PCI I/O1",
++ .start = RALINK_PCI_IO_MAP_BASE,
++ .end = (u32)((RALINK_PCI_IO_MAP_BASE + (unsigned char *)0x0ffff)),
++ .flags = IORESOURCE_IO,
++};
++
++struct pci_controller rt2880_controller = {
++ .pci_ops = &rt2880_pci_ops,
++ .mem_resource = &rt2880_res_pci_mem1,
++ .io_resource = &rt2880_res_pci_io1,
++ .mem_offset = 0x00000000UL,
++ .io_offset = 0x00000000UL,
++};
++
++void __inline__ read_config(unsigned long bus, unsigned long dev, unsigned long func, unsigned long reg, unsigned long *val)
++{
++ unsigned long address_reg, data_reg, address;
++
++ address_reg = RALINK_PCI_CONFIG_ADDR;
++ data_reg = RALINK_PCI_CONFIG_DATA_VIRTUAL_REG;
++
++ /* set addr */
++#if defined (CONFIG_RALINK_RT2883)
++ address = (bus << 24) | (dev << 19) | (func << 16) | (reg & 0xfc);
++#elif defined (CONFIG_RALINK_RT3883)
++ address = (bus << 16) | (dev << 11) | (func << 8) | (reg& 0xfc) | 0x80000000 ;
++#elif defined (CONFIG_RALINK_RT6855)
++ address = (bus << 16) | (dev << 11) | (func << 8) | (reg& 0xfc) | 0x80000000 ;
++#elif defined (CONFIG_RALINK_RT6855A)
++ address = (bus << 24) | (dev << 19) | (func << 16) | (reg& 0xfc);
++#else
++ address = (bus << 16) | (dev << 11) | (func << 8) | (reg & 0xfc) | 0x80000000 ;
++#endif
++
++ /* start the configuration cycle */
++ MV_WRITE(address_reg, address);
++ /* read the data */
++ MV_READ(data_reg, val);
++ return;
++}
++
++void __inline__ write_config(unsigned long bus, unsigned long dev, unsigned long func, unsigned long reg, unsigned long val)
++{
++ unsigned long address_reg, data_reg, address;
++
++ address_reg = RALINK_PCI_CONFIG_ADDR;
++ data_reg = RALINK_PCI_CONFIG_DATA_VIRTUAL_REG;
++
++ /* set addr */
++#if defined (CONFIG_RALINK_RT2883)
++ address = (bus << 24) | (dev << 19) | (func << 16) | (reg & 0xfc);
++#elif defined (CONFIG_RALINK_RT3883)
++ address = (bus << 16) | (dev << 11) | (func << 8) | (reg& 0xfc) | 0x80000000 ;
++#elif defined (CONFIG_RALINK_RT6855)
++ address = (bus << 16) | (dev << 11) | (func << 8) | (reg& 0xfc) | 0x80000000 ;
++#elif defined (CONFIG_RALINK_RT6855A)
++ address = (bus << 24) | (dev << 19) | (func << 16) | (reg& 0xfc);
++#else
++ address = (bus << 16) | (dev << 11) | (func << 8) | (reg & 0xfc) | 0x80000000 ;
++#endif
++ /* start the configuration cycle */
++ MV_WRITE(address_reg, address);
++ /* read the data */
++ MV_WRITE(data_reg, val);
++ return;
++}
++
++
++int pcibios_map_irq(const struct pci_dev *d, u8 slot, u8 pin)
++{
++ struct pci_dev *dev = (struct pci_dev *)d;
++ u16 cmd;
++ u32 val;
++ struct resource *res;
++ int i;
++#ifdef CONFIG_RALINK_RT2883
++ if (dev->bus->number > 1) {
++ printk("bus>1\n");
++ return 0;
++ }
++ if (slot > 0) {
++ printk("slot=%d >0\n", slot);
++ return 0;
++ }
++#elif defined (CONFIG_RALINK_RT2880)
++ if (dev->bus->number != 0) {
++ return 0;
++ }
++#else
++#endif
++
++ printk("** bus= %x, slot=0x%x\n",dev->bus->number, slot);
++#ifdef CONFIG_RALINK_RT3883
++ if((dev->bus->number ==0) && (slot == 0)) {
++ RALINK_PCI0_BAR0SETUP_ADDR = 0x03FF0001; //open 3FF:64M; ENABLE
++ RALINK_PCI0_BAR0SETUP_ADDR = 0x03FF0001; //open 3FF:64M; ENABLE
++ RALINK_PCI1_BAR0SETUP_ADDR = 0x03FF0001; //open 3FF:64M; ENABLE
++ RALINK_PCI1_BAR0SETUP_ADDR = 0x03FF0001; //open 3FF:64M; ENABLE
++ write_config(0, 0, 0, PCI_BASE_ADDRESS_0, MEMORY_BASE);
++ read_config(0, 0, 0, PCI_BASE_ADDRESS_0, (unsigned long *)&val);
++ printk("BAR0 at slot 0 = %x\n", val);
++// dev->irq = 0;
++ printk("bus=0, slot = 0x%x\n", slot);
++ res = &dev->resource[0];
++ res->start = MEMORY_BASE;
++ res->end = MEMORY_BASE + 0x01ffffff;
++ for(i=0;i<16;i++){
++ read_config(0, 0, 0, i<<2, (unsigned long *)&val);
++ printk("P2P(PCI) 0x%02x = %08x\n", i<<2, val);
++ }
++ dev->irq = 0;
++ }else if((dev->bus->number ==0) && (slot == 0x1)){
++ write_config(0, 1, 0, 0x1c, 0x00000101);
++ for(i=0;i<16;i++){
++ read_config(0, 1, 0, i<<2, (unsigned long *)&val);
++ printk("P2P(PCIe) 0x%02x = %08x\n", i<<2, val);
++ }
++ }else if((dev->bus->number ==0) && (slot == 0x11)){
++ printk("bus=0, slot = 0x%x\n", slot);
++ for(i=0;i<16;i++){
++ read_config(0, 0x11, 0, i<<2, (unsigned long *)&val);
++ printk("dev I(PCI) 0x%02x = %08x\n", i<<2, val);
++ }
++ dev->irq = 2;
++ }else if((dev->bus->number ==0) && (slot == 0x12)){
++ printk("bus=0, slot = 0x%x\n", slot);
++ for(i=0;i<16;i++){
++ read_config(0, 0x12, 0, i<<2, (unsigned long *)&val);
++ printk("dev II(PCI) 0x%02x = %08x\n", i<<2, val);
++ }
++ dev->irq = 15;
++ }else if((dev->bus->number ==1) ){
++ printk("bus=1, slot = 0x%x\n", slot);
++ for(i=0;i<16;i++){
++ read_config(1, 0, 0, i<<2, (unsigned long *)&val);
++ printk("dev III(PCIe) 0x%02x = %08x\n", i<<2, val);
++ }
++ dev->irq = 16;
++ }else{
++ return 0;
++ }
++#elif defined(CONFIG_RALINK_RT6855) || defined (CONFIG_RALINK_RT6855A)
++ if((dev->bus->number ==0) && (slot == 0)) {
++ RALINK_PCI0_BAR0SETUP_ADDR = 0x7FFF0001; //open 7FFF:2G
++ write_config(0, 0, 0, PCI_BASE_ADDRESS_0, MEMORY_BASE);
++ read_config(0, 0, 0, PCI_BASE_ADDRESS_0, (unsigned long *)&val);
++ //write_config(0, 0, 0, 0x1c, 0x00000101);
++ printk("BAR0 at slot 0 = %x\n", val);
++ printk("bus=0x%x, slot = 0x%x\n",dev->bus->number, slot);
++#if 0
++ res = &dev->resource[0];
++ res->start = MEMORY_BASE;
++ res->end = MEMORY_BASE + 0x03ffffff;
++ //dev->irq = RALINK_INT_PCIE0;
++ for(i=0;i<16;i++){
++ read_config(0, 0, 0, i<<2, &val);
++ printk("P2P(PCIe0) 0x%02x = %08x\n", i<<2, val);
++ }
++#endif
++ }else if((dev->bus->number ==0) && (slot == 0x1)){
++ RALINK_PCI1_BAR0SETUP_ADDR = 0x7FFF0001; //open 7FFF:2G
++ write_config(0, 1, 0, PCI_BASE_ADDRESS_0, MEMORY_BASE);
++ read_config(0, 1, 0, PCI_BASE_ADDRESS_0, (unsigned long *)&val);
++ //write_config(0, 1, 0, 0x1c, 0x00000101);
++ printk("BAR0 at slot 1 = %x\n", val);
++ printk("bus=0x%x, slot = 0x%x\n",dev->bus->number, slot);
++#if 0
++ res = &dev->resource[0];
++ res->start = MEMORY_BASE;
++ res->end = MEMORY_BASE + 0x03ffffff;
++ //dev->irq = RALINK_INT_PCIE1;
++ for(i=0;i<16;i++){
++ read_config(0, 1, 0, i<<2, &val);
++ printk("P2P(PCIe1) 0x%02x = %08x\n", i<<2, val);
++ }
++#endif
++ }else if((dev->bus->number ==1) && (slot == 0x0)){
++ printk("bus=0x%x, slot = 0x%x\n",dev->bus->number, slot);
++ dev->irq = RALINK_INT_PCIE0;
++#if 0
++ for(i=0;i<16;i++){
++ read_config(1, 0, 0, i<<2, &val);
++ printk("dev I(PCIe0) 0x%02x = %08x\n", i<<2, val);
++ }
++#endif
++ }else if((dev->bus->number ==1) && (slot == 0x1)){
++ printk("bus=0x%x, slot = 0x%x\n",dev->bus->number, slot);
++ dev->irq = RALINK_INT_PCIE1;
++ }else if((dev->bus->number ==2) && (slot == 0x0)){
++ printk("bus=0x%x, slot = 0x%x\n",dev->bus->number, slot);
++ dev->irq = RALINK_INT_PCIE1;
++#if 0
++ for(i=0;i<16;i++){
++ read_config(2, 0, 0, i<<2, &val);
++ printk("dev II(PCIe1) 0x%02x = %08x\n", i<<2, val);
++ }
++#endif
++ }else if((dev->bus->number ==2) && (slot == 0x1)){
++ printk("bus=0x%x, slot = 0x%x\n",dev->bus->number, slot);
++ dev->irq = RALINK_INT_PCIE1;
++ }else{
++ printk("bus=0x%x, slot = 0x%x\n",dev->bus->number, slot);
++ return 0;
++ }
++#elif defined (CONFIG_RALINK_RT2883)
++ if((dev->bus->number ==0) && (slot == 0)) {
++ RALINK_PCI_BAR0SETUP_ADDR = 0x01FF0001; //open 1FF:32M; ENABLE
++ write_config(0, 0, 0, PCI_BASE_ADDRESS_0, MEMORY_BASE);
++ read_config(0, 0, 0, PCI_BASE_ADDRESS_0, &val);
++ printk("BAR0 at slot 0 = %x\n", val);
++// dev->irq = 0;
++ printk("bus=0, slot = 0x%x\n", slot);
++ res = &dev->resource[0];
++ res->start = MEMORY_BASE;
++ res->end = MEMORY_BASE + 0x01ffffff;
++ for(i=0;i<16;i++){
++ read_config(0, 0, 0, i<<2, &val);
++ printk("pci-to-pci 0x%02x = %08x\n", i<<2, val);
++ }
++ dev->irq = 0;
++ }else if((dev->bus->number ==1)){
++ printk("bus=1, slot = 0x%x\n", slot);
++ for(i=0;i<16;i++){
++ read_config(1, slot, 0, (i)<<2, &val);
++ printk("bus 1 dev %d fun 0: 0x%02x = %08x\n", slot, i<<2, val);
++ }
++ dev->irq = 2;
++ }else{
++ return 0;
++ }
++#else //RT2880
++ if(slot == 0) {
++ printk("*************************************************************\n");
++ RALINK_PCI_BAR0SETUP_ADDR = 0x07FF0001;
++ printk("MEMORY_BASE = %x\n", MEMORY_BASE);
++ write_config(0, 0, 0, PCI_BASE_ADDRESS_0, MEMORY_BASE);
++ read_config(0, 0, 0, PCI_BASE_ADDRESS_0, &val);
++ dev->irq = 0;
++ res = &dev->resource[0];
++ res->start = 0x08000000;
++ res->end = 0x09ffffff;
++ printk("BAR0 at slot 0 = %x\n", val);
++ }else if(slot ==0x11){
++ dev->irq = 2;
++ }else if(slot==0x12){
++ dev->irq = 15;
++ }else{
++ return 0;
++ }
++#endif
++
++ for(i=0;i<6;i++){
++ res = &dev->resource[i];
++ printk("res[%d]->start = %x\n", i, res->start);
++ printk("res[%d]->end = %x\n", i, res->end);
++ }
++
++ pci_write_config_byte(dev, PCI_CACHE_LINE_SIZE, 0x14); //configure cache line size 0x14
++ pci_write_config_byte(dev, PCI_LATENCY_TIMER, 0xFF); //configure latency timer 0x10
++ pci_read_config_word(dev, PCI_COMMAND, &cmd);
++//FIXME
++#if defined(CONFIG_RALINK_RT2883) || defined(CONFIG_RALINK_RT3883) || defined(CONFIG_RALINK_RT6855) || defined(CONFIG_RALINK_RT6855A)
++ cmd = cmd | PCI_COMMAND_MASTER | PCI_COMMAND_IO | PCI_COMMAND_MEMORY;
++#else
++ cmd = cmd | PCI_COMMAND_MASTER | PCI_COMMAND_IO | PCI_COMMAND_MEMORY |
++ PCI_COMMAND_INVALIDATE | PCI_COMMAND_FAST_BACK | PCI_COMMAND_SERR |
++ PCI_COMMAND_WAIT | PCI_COMMAND_PARITY;
++#endif
++ pci_write_config_word(dev, PCI_COMMAND, cmd);
++ pci_write_config_byte(dev, PCI_INTERRUPT_LINE, dev->irq);
++ //pci_write_config_byte(dev, PCI_INTERRUPT_PIN, dev->irq);
++ return (dev->irq);
++}
++
++int init_ralink_pci(void)
++{
++ unsigned long val = 0;
++#if 0 /*CONFIG_RALINK_RT6855*/
++ int i;
++#endif
++
++#if defined(CONFIG_PCIE_ONLY) || defined(CONFIG_PCIE_PCI_CONCURRENT)
++ RALINK_RSTCTRL = (RALINK_RSTCTRL | RALINK_PCIE_RST);
++ RALINK_SYSCFG1 &= ~(0x30);
++ RALINK_SYSCFG1 |= (2<<4);
++ RALINK_PCIE_CLK_GEN &= 0x7fffffff;
++ RALINK_PCIE_CLK_GEN1 &= 0x80ffffff;
++ RALINK_PCIE_CLK_GEN1 |= 0xa << 24;
++ RALINK_PCIE_CLK_GEN |= 0x80000000;
++ mdelay(50);
++ RALINK_RSTCTRL = (RALINK_RSTCTRL & ~RALINK_PCIE_RST);
++#endif
++
++#ifdef CONFIG_RALINK_RT3883
++#if 0
++ printk("before\n");
++ printk("RALINK_GPIOMODE = %x\n", RALINK_GPIOMODE);
++ printk("RALINK_SYSCFG1 = %x\n", RALINK_SYSCFG1);
++ printk("RALINK_RSTCTRL = %x\n", RALINK_RSTCTRL);
++ printk("RALINK_CLKCFG1 = %x\n", RALINK_CLKCFG1);
++ printk("RALINK_PCIE_CLK_GEN= %x\n", RALINK_PCIE_CLK_GEN);
++ printk("RALINK_PCIE_CLK_GEN1= %x\n", RALINK_PCIE_CLK_GEN1);
++ printk("**************************\n");
++#endif
++
++#ifdef CONFIG_PCI_ONLY
++//PCI host only, 330T
++ RALINK_GPIOMODE = ((RALINK_GPIOMODE & (~(0x3800))) | PCI_SLOTx2);
++ RALINK_SYSCFG1 = (RALINK_SYSCFG1 | RALINK_PCI_HOST_MODE_EN | RALINK_PCIE_RC_MODE_EN);
++ RALINK_RSTCTRL = (RALINK_RSTCTRL | RALINK_PCIE_RST);
++ RALINK_CLKCFG1 = (RALINK_CLKCFG1 & ~RALINK_PCIE_CLK_EN);
++#elif defined (CONFIG_PCIE_ONLY)
++//PCIe RC only, 220T
++ RALINK_SYSCFG1 = (RALINK_SYSCFG1 | RALINK_PCIE_RC_MODE_EN | RALINK_PCI_HOST_MODE_EN);
++ RALINK_RSTCTRL = (RALINK_RSTCTRL | RALINK_PCI_RST);
++ RALINK_CLKCFG1 = (RALINK_CLKCFG1 & ~RALINK_PCI_CLK_EN);
++#elif defined (CONFIG_PCIE_PCI_CONCURRENT)
++//PCIe PCI co-exist
++ RALINK_GPIOMODE = ((RALINK_GPIOMODE & ~(0x3800)) | PCI_SLOTx2);
++ RALINK_SYSCFG1 = (RALINK_SYSCFG1 | RALINK_PCI_HOST_MODE_EN | RALINK_PCIE_RC_MODE_EN);
++#endif
++ mdelay(500);
++
++#if 0
++ printk("after\n");
++ printk("RALINK_GPIOMODE = %x\n", RALINK_GPIOMODE);
++ printk("RALINK_SYSCFG1 = %x\n", RALINK_SYSCFG1);
++ printk("RALINK_RSTCTRL = %x\n", RALINK_RSTCTRL);
++ printk("RALINK_CLKCFG1 = %x\n", RALINK_CLKCFG1);
++ printk("RALINK_PCIE_CLK_GEN= %x\n", RALINK_PCIE_CLK_GEN);
++ printk("RALINK_PCIE_CLK_GEN1= %x\n", RALINK_PCIE_CLK_GEN1);
++ printk("**************************\n");
++#endif
++#endif
++
++#ifdef CONFIG_RALINK_RT2880
++ //pci_probe_only = 1;
++ RALINK_PCI_PCICFG_ADDR = 0;
++#elif defined (CONFIG_RALINK_RT2883)
++ RALINK_PCI_PCICFG_ADDR = 0;
++#elif defined (CONFIG_RALINK_RT3883)
++
++#ifdef CONFIG_PCIE_ONLY
++ RALINK_PCI_PCICFG_ADDR = 0;
++ //RALINK_PCI_PCICFG_ADDR |= (1<<16);
++#elif defined (CONFIG_PCI_ONLY)
++ RALINK_PCI_PCICFG_ADDR = 0;
++ RALINK_PCI_PCICFG_ADDR |= (1<<16);
++#elif defined (CONFIG_PCIE_PCI_CONCURRENT)
++ RALINK_PCI_PCICFG_ADDR = 0;
++ RALINK_PCI_PCICFG_ADDR |= (1<<16);
++#endif
++#elif defined(CONFIG_RALINK_RT6855)
++ //RALINK_PCI_PCICFG_ADDR = 0;
++ //RALINK_PCI_PCICFG_ADDR |= (1<<20); //DEV0 = 0; DEV1 = 1
++ printk("start PCIe register access\n");
++ RALINK_PCI_PCICFG_ADDR &= ~(1<<1); //de-assert PERST
++ //printk("RALINK_PCI_PCICFG_ADDR= %x\n", RALINK_PCI_PCICFG_ADDR);
++ //RALINK_RSTCTRL = (RALINK_RSTCTRL | RALINK_PCIE1_RST);
++ //printk("RALINK_RSTCTRL= %x\n", RALINK_RSTCTRL);
++#elif defined(CONFIG_RALINK_RT6855A)
++ printk("start PCIe register access\n");
++#if defined(CONFIG_RT6855A_PCIE_PORT0_ENABLE)
++ //PCI Control Register: Port1(bit22) disable
++ *((unsigned long *)(0xbfb00088)) &= ~(1<<22);
++ mdelay(1);
++ //assert PCIe RC1 reset signal
++ *((unsigned long *)(0xbfb00834)) |= ( 1<<27 );
++ //disable reference clock of dev1
++ *((unsigned long *)(0xbfb00090)) &= ~( 1<<3 );
++ printk("0xbfb00834 = %x\n", *((unsigned long *)(0xbfb00834)));
++ printk("0xbfb00088 = %x\n", *((unsigned long *)(0xbfb00088)));
++
++
++#elif defined(CONFIG_RT6855A_PCIE_PORT01_ENABLE)
++#endif
++ //PCIe Configuration and Status Register:PCIeRST
++ RALINK_PCI_PCICFG_ADDR &= ~(1<<1);
++#if 0
++ mdelay(500);
++ //for FPGA only
++ //port0
++ *((unsigned long *)(0xbfbc0028)) = 0x60068880;
++ *((unsigned long *)(0xbfbc0004)) = 0x08000002;
++ *((unsigned long *)(0xbfbc0008)) = 0x00000700;
++ *((unsigned long *)(0xbfbc0000)) = 0x00160106;
++ //port1
++ *((unsigned long *)(0xbfbc0028)) = 0x80068880;
++ *((unsigned long *)(0xbfbc0004)) = 0x08000002;
++ *((unsigned long *)(0xbfbc0008)) = 0x00000700;
++ *((unsigned long *)(0xbfbc0000)) = 0x00160106;
++#endif
++#endif
++ mdelay(500);
++
++ //printk("RALINK_PCI_PCICFG_ADDR = %x\n", RALINK_PCI_PCICFG_ADDR);
++
++#ifdef CONFIG_RALINK_RT3883
++ printk("\n*************** Ralink PCIe RC mode *************\n");
++ mdelay(500);
++ if(RALINK_SYSCFG1 & RALINK_PCIE_RC_MODE_EN){
++ if(( RALINK_PCI1_STATUS & 0x1) == 0)
++ {
++ printk(" RALINK_PCI1_STATUS = %x\n", RALINK_PCI1_STATUS );
++ for(i=0;i<16;i++){
++ read_config(0, 1, 0, i<<2, &val);
++ printk("pci-to-pci 0x%02x = %08x\n", i<<2, (int)val);
++ }
++#ifdef CONFIG_PCIE_ONLY
++ printk("reset PCIe and turn off PCIe clock\n");
++ RALINK_RSTCTRL = (RALINK_RSTCTRL | RALINK_PCIE_RST);
++ RALINK_RSTCTRL = (RALINK_RSTCTRL & ~RALINK_PCIE_RST);
++ RALINK_CLKCFG1 = (RALINK_CLKCFG1 & ~RALINK_PCIE_CLK_EN);
++ printk("RALINK_CLKCFG1 = %x\n", RALINK_CLKCFG1);
++ //cgrstb, cgpdb, pexdrven0, pexdrven1, cgpllrstb, cgpllpdb, pexclken
++ RALINK_PCIE_CLK_GEN &= 0x0fff3f7f;
++ printk("RALINK_PCIE_CLK_GEN= %x\n", RALINK_PCIE_CLK_GEN);
++ return 0;
++#else
++ RALINK_CLKCFG1 = (RALINK_CLKCFG1 & ~RALINK_PCIE_CLK_EN);
++#endif
++ }
++ }
++ if(RALINK_SYSCFG1 & RALINK_PCI_HOST_MODE_EN){
++ RALINK_PCI_ARBCTL = 0x79;
++ }
++
++#elif defined(CONFIG_RALINK_RT6855)
++ printk("\n*************** RT6855 PCIe RC mode *************\n");
++ mdelay(500);
++ if(( RALINK_PCI0_STATUS & 0x1) == 0)
++ {
++ //RALINK_RSTCTRL = (RALINK_RSTCTRL | RALINK_PCIE0_RST);
++ RALINK_CLKCFG1 = (RALINK_CLKCFG1 & ~RALINK_PCIE0_CLK_EN);
++ printk("PCIE0 no card, disable it(RST&CLK)\n");
++ pcie0_disable=1;
++ }
++ if(( RALINK_PCI1_STATUS & 0x1) == 0)
++ {
++ //RALINK_RSTCTRL = (RALINK_RSTCTRL | RALINK_PCIE1_RST);
++ RALINK_CLKCFG1 = (RALINK_CLKCFG1 & ~RALINK_PCIE1_CLK_EN);
++ printk("PCIE1 no card, disable it(RST&CLK)\n");
++ pcie1_disable=1;
++ }else{
++ if(pcie0_disable==1){
++ /* pcie0 no card, pcie1 has card */
++ //James want to go back, next two line
++ //RALINK_PCI_PCICFG_ADDR &= ~(0xff<<16);
++ //RALINK_PCI_PCICFG_ADDR |= 1<<16;
++ //printk("***RALINK_PCI_PCICFG_ADDR= %x\n", RALINK_PCI_PCICFG_ADDR);
++ }
++ }
++#elif defined (CONFIG_RALINK_RT6855A)
++ printk("\n*************** RT6855A PCIe RC mode *************\n");
++ mdelay(500);
++ if(( RALINK_PCI0_STATUS & 0x1) == 0)
++ {
++ //assert PCIe RC0 reset signal
++ //*((unsigned long *)(0xbfb00834)) |= ( 1<<26 );
++ *((unsigned long *)(0xbfb00088)) &= ~( 1<<23 );
++ printk("PCIE0 no card, disable it\n");
++ pcie0_disable=1;
++ }
++ if(( RALINK_PCI1_STATUS & 0x1) == 0)
++ {
++ //PCI Control Register: Port1(bit22) disable
++ *((unsigned long *)(0xbfb00088)) &= ~(1<<22);
++ mdelay(1);
++ //assert PCIe RC1 reset signal
++ *((unsigned long *)(0xbfb00834)) |= ( 1<<27 );
++ mdelay(1);
++ //disable reference clock of dev1
++ *((unsigned long *)(0xbfb00090)) &= ~( 1<<3 );
++ printk("PCIE1 no card, disable it(RST&CLK)\n");
++ pcie1_disable=1;
++ }else{
++ if(pcie0_disable==1){
++ /* pcie0 no card, pcie1 has card */
++ RALINK_PCI_PCICFG_ADDR &= ~(0xff<<16);
++ RALINK_PCI_PCICFG_ADDR |= 1<<16;
++ printk("***RALINK_PCI_PCICFG_ADDR= %x\n", RALINK_PCI_PCICFG_ADDR);
++ }
++ }
++#if 0
++ printk("\n*************** RT6855A PCIe RC mode *************\n");
++ mdelay(1000);
++#if defined(CONFIG_RT6855A_PCIE_PORT0_ENABLE)
++ if((RALINK_PCI0_STATUS & 0x1)==0){
++ printk("PCIE0 no card\n");
++ return 0;
++ }
++#elif defined(CONFIG_RT6855A_PCIE_PORT01_ENABLE)
++ if((RALINK_PCI0_STATUS & 0x1)==0){
++ printk("PCIE0 no card\n");
++ }else{
++ printk("PCIE0 card detected\n");
++ }
++ if((RALINK_PCI1_STATUS & 0x1)==0){
++ printk("PCIE1 no card\n");
++ }else{
++ printk("PCIE1 card detected\n");
++ }
++ if(((RALINK_PCI0_STATUS & 0x1)==0) && ((RALINK_PCI1_STATUS & 0x1)==0)){
++ printk("PCIE0&1 both no card\n");
++ return 0;
++ }
++#endif
++#endif
++#elif defined (CONFIG_RALINK_RT2883)
++ printk("\n*************** Ralink PCIe RC mode *************\n");
++ mdelay(500);
++ if(( RALINK_PCI_STATUS & 0x1) == 0)
++ {
++ printk(" RALINK_PCI_STATUS = %x\n", RALINK_PCI_STATUS );
++ printk("************No PCIE device**********\n");
++ for(i=0;i<16;i++){
++ read_config(0, 0, 0, i<<2, &val);
++ printk("pci-to-pci 0x%02x = %08x\n", i<<2, val);
++ }
++ return 0;
++ }
++#else
++ for(i=0;i<0xfffff;i++);
++ RALINK_PCI_ARBCTL = 0x79;
++#endif
++ //printk(" RALINK_PCI_ARBCTL = %x\n", RALINK_PCI_ARBCTL);
++
++/*
++ ioport_resource.start = rt2880_res_pci_io1.start;
++ ioport_resource.end = rt2880_res_pci_io1.end;
++*/
++
++ RALINK_PCI_MEMBASE = 0xffffffff; //RALINK_PCI_MM_MAP_BASE;
++ RALINK_PCI_IOBASE = RALINK_PCI_IO_MAP_BASE;
++
++#ifdef CONFIG_RALINK_RT2880
++ RALINK_PCI_BAR0SETUP_ADDR = 0x07FF0000; //open 1FF:32M; DISABLE
++ RALINK_PCI_IMBASEBAR0_ADDR = MEMORY_BASE;
++ RALINK_PCI_ID = 0x08021814;
++ RALINK_PCI_CLASS = 0x00800001;
++ RALINK_PCI_SUBID = 0x28801814;
++#elif defined (CONFIG_RALINK_RT2883)
++ RALINK_PCI_BAR0SETUP_ADDR = 0x01FF0000; //open 1FF:32M; DISABLE
++ RALINK_PCI_IMBASEBAR0_ADDR = MEMORY_BASE;
++ RALINK_PCI_ID = 0x08021814;
++ RALINK_PCI_CLASS = 0x06040001;
++ RALINK_PCI_SUBID = 0x28801814;
++#elif defined (CONFIG_RALINK_RT3883)
++ //PCI
++ RALINK_PCI0_BAR0SETUP_ADDR = 0x03FF0000; //open 3FF:64M; DISABLE
++ RALINK_PCI0_IMBASEBAR0_ADDR = MEMORY_BASE;
++ RALINK_PCI0_ID = 0x08021814;
++ RALINK_PCI0_CLASS = 0x00800001;
++ RALINK_PCI0_SUBID = 0x28801814;
++ //PCIe
++ RALINK_PCI1_BAR0SETUP_ADDR = 0x03FF0000; //open 3FF:64M; DISABLE
++ RALINK_PCI1_IMBASEBAR0_ADDR = MEMORY_BASE;
++ RALINK_PCI1_ID = 0x08021814;
++ RALINK_PCI1_CLASS = 0x06040001;
++ RALINK_PCI1_SUBID = 0x28801814;
++#elif defined (CONFIG_RALINK_RT6855) || defined (CONFIG_RALINK_RT6855A)
++ //PCIe0
++ //if(pcie0_disable!=1){
++ RALINK_PCI0_BAR0SETUP_ADDR = 0x7FFF0001; //open 7FFF:2G
++ RALINK_PCI0_IMBASEBAR0_ADDR = MEMORY_BASE;
++ RALINK_PCI0_ID = 0x08021814;
++ RALINK_PCI0_CLASS = 0x06040001;
++ RALINK_PCI0_SUBID = 0x28801814;
++ //}
++ //PCIe1
++ //if(pcie1_disable!=1){
++ RALINK_PCI1_BAR0SETUP_ADDR = 0x7FFF0001; //open 7FFF:2G
++ RALINK_PCI1_IMBASEBAR0_ADDR = MEMORY_BASE;
++ RALINK_PCI1_ID = 0x08021814;
++ RALINK_PCI1_CLASS = 0x06040001;
++ RALINK_PCI1_SUBID = 0x28801814;
++ //}
++#endif
++
++
++#ifdef CONFIG_RALINK_RT3883
++ RALINK_PCI_PCIMSK_ADDR = 0x001c0000; // enable pcie/pci interrupt
++#elif defined (CONFIG_RALINK_RT6855) || defined (CONFIG_RALINK_RT6855A)
++ //if(pcie0_disable!=1){
++ RALINK_PCI_PCIMSK_ADDR |= (1<<20); // enable pcie0 interrupt
++ //}
++ //if(pcie1_disable!=1){
++ RALINK_PCI_PCIMSK_ADDR |= (1<<21); // enable pcie1 interrupt
++ //}
++#else
++ RALINK_PCI_PCIMSK_ADDR = 0x000c0000; // enable pci interrupt
++#endif
++
++#ifdef CONFIG_RALINK_RT3883
++ //PCIe
++ read_config(0, 1, 0, 0x4, &val);
++ write_config(0, 1, 0, 0x4, val|0x7);
++ //PCI
++ read_config(0, 0, 0, 0x4, &val);
++ write_config(0, 0, 0, 0x4, val|0x7);
++#elif defined (CONFIG_RALINK_RT6855) || defined (CONFIG_RALINK_RT6855A)
++ //PCIe0
++ if(pcie0_disable==0 || pcie1_disable==0){
++ read_config(0, 0, 0, 0x4, &val);
++ write_config(0, 0, 0, 0x4, val|0x7);
++ //printk("%s %s %d\n", __FILE__, __FUNCTION__, __LINE__);
++ }
++ //PCIe1
++ if(pcie0_disable==0 && pcie1_disable==0){
++ read_config(0, 1, 0, 0x4, &val);
++ write_config(0, 1, 0, 0x4, val|0x7);
++ //printk("%s %s %d\n", __FILE__, __FUNCTION__, __LINE__);
++ }
++#elif defined (CONFIG_RALINK_RT2883)
++ read_config(0, 0, 0, 0x4, &val);
++ write_config(0, 0, 0, 0x4, val|0x7);
++ //FIXME
++ ////write_config(0, 0, 0, 0x18, 0x10100);
++ //write_config(0, 0, 0, PCI_BASE_ADDRESS_0, MEMORY_BASE);
++ //read_config(0, 0, 0, PCI_BASE_ADDRESS_0, &val);
++ ////printk("BAR0 at slot 0 = %x\n", val);
++#else
++ write_config(0, 0, 0, PCI_BASE_ADDRESS_0, MEMORY_BASE);
++ read_config(0, 0, 0, PCI_BASE_ADDRESS_0, &val);
++ printk("BAR0 at slot 0 = %x\n", val);
++#endif
++#if 0 /*CONFIG_RALINK_RT6855*/
++
++ for(i=0;i<16;i++){
++ read_config(0, 0, 0, i<<2, &val);
++ printk("PCI-to-PCI bridge0 0x%02x = %08x\n", i<<2, (unsigned int)val);
++ }
++ for(i=0;i<16;i++){
++ read_config(0, 1, 0, i<<2, &val);
++ printk("PCI-to-PCI bridge1 0x%02x = %08x\n", i<<2, (unsigned int)val);
++ }
++#endif
++ register_pci_controller(&rt2880_controller);
++ return 0;
++
++}
++#ifndef CONFIG_PCIE_PCI_NONE
++arch_initcall(init_ralink_pci);
++#endif
++
++/* Do platform specific device initialization at pci_enable_device() time */
++int pcibios_plat_dev_init(struct pci_dev *dev)
++{
++ pci_cache_line_size = 32 >> 2;
++ return 0;
++}
++
++struct pci_fixup pcibios_fixups[] = {
++// {PCI_ANY_ID, PCI_ANY_ID, pcibios_fixup_resources },
++ {0}
++};
++//DECLARE_PCI_FIXUP_FINAL(PCI_ANY_ID, PCI_ANY_ID, pcibios_fixup_resources)
++#endif /* CONFIG_PCI */
+diff --git a/arch/mips/ralink/reset.c b/arch/mips/ralink/reset.c
+index 8126f1260407..390cff1c58d7 100644
+--- a/arch/mips/ralink/reset.c
++++ b/arch/mips/ralink/reset.c
+@@ -82,6 +82,21 @@ void ralink_rst_init(void)
+ reset_controller_register(&reset_dev);
+ }
+
++#define CR_TIMER_BASE 0xBFBF0100
++#define CR_TIMER_CTL ((char*)(CR_TIMER_BASE + 0x00))
++#define CR_TIMER0_LDV (CR_TIMER_BASE + 0x04)
++
++#define TIMER_ENABLE 1
++#define TIMER_DISABLE 0
++#define TIMER_TOGGLEMODE 1
++#define TIMER_INTERVALMODE 0
++#define TIMER_TICKENABLE 1
++#define TIMER_TICKDISABLE 0
++#define TIMER_WDENABLE 1
++#define TIMER_WDDISABLE 0
++#define TIMER_HALTENABLE 1
++#define TIMER_HALTDISABLE 0
++
+ static void ralink_restart(char *command)
+ {
+ if (IS_ENABLED(CONFIG_PCI)) {
+@@ -90,7 +105,14 @@ static void ralink_restart(char *command)
+ }
+
+ local_irq_disable();
+- rt_sysc_w32(RSTCTL_RESET_SYSTEM, SYSC_REG_RESET_CTRL);
++ if (0) {
++ rt_sysc_w32(RSTCTL_RESET_SYSTEM, SYSC_REG_RESET_CTRL);
++ } else {
++ const u8 timer_no = 5;
++#define SYS_HCLK (23333/100)
++ writel((100 /* ms */ * SYS_HCLK) * 1000 / 2, (char*)(CR_TIMER0_LDV+timer_no*0x08));
++ writel((TIMER_ENABLE << timer_no) | (TIMER_WDENABLE << 25), CR_TIMER_CTL);
++ }
+ unreachable();
+ }
+
+diff --git a/arch/mips/ralink/rt6855.c b/arch/mips/ralink/rt6855.c
+new file mode 100644
+index 000000000000..4bdb492c6ba1
+--- /dev/null
++++ b/arch/mips/ralink/rt6855.c
+@@ -0,0 +1,55 @@
++// SPDX-License-Identifier: GPL-2.0-or-later
++/*
++ * Copyright (C) 2016 Imagination Technologies
++ * Author: Paul Burton <paul.burton at mips.com>
++ */
++
++#include <linux/clk.h>
++#include <linux/clocksource.h>
++#include <linux/init.h>
++#include <linux/irqchip.h>
++#include <linux/of_clk.h>
++#include <linux/of_fdt.h>
++#include <linux/serial_reg.h>
++
++#include <asm/bootinfo.h>
++#include <asm/fw/fw.h>
++#include <asm/irq_cpu.h>
++#include <asm/machine.h>
++#include <asm/mips-cps.h>
++#include <asm/prom.h>
++#include <asm/smp-ops.h>
++#include <asm/time.h>
++
++#include <asm/mach-ralink/ralink_regs.h>
++
++#include "common.h"
++
++void prom_soc_init(struct ralink_soc_info *soc_info)
++{
++ soc_info->mem_size_min = 64;
++ soc_info->mem_size_max = 64;
++ soc_info->compatible = "ralink,rt6855-soc";
++ soc_info->mem_base = 0x20000;
++ ralink_soc = RT6855_SOC;
++}
++
++void __init ralink_of_remap(void)
++{
++ rt_sysc_membase = plat_of_remap_node("ralink,rt6855-sysc");
++ rt_memc_membase = plat_of_remap_node("ralink,rt6855-memc");
++
++ if (!rt_sysc_membase || !rt_memc_membase)
++ panic("Failed to remap core resources");
++}
++
++void __init ralink_clk_init(void)
++{
++ unsigned long sys_rate = 233333333;
++
++ ralink_clk_add("cpu", 700000000);
++ ralink_clk_add("1fbf0100.watchdog", sys_rate);
++ ralink_clk_add("1fbf0000.uart", 40000000);
++ ralink_clk_add("1fb50000.ethernet", 700000000 / 2);
++ ralink_clk_add("1fbc0b00.spi", sys_rate);
++}
+diff --git a/arch/mips/ralink/rt_mmap.h b/arch/mips/ralink/rt_mmap.h
+new file mode 100644
+index 000000000000..3f72bb1b3879
+--- /dev/null
++++ b/arch/mips/ralink/rt_mmap.h
+@@ -0,0 +1,551 @@
++/**************************************************************************
++ *
++ * BRIEF MODULE DESCRIPTION
++ * register definition for Ralink RT-series SoC
++ *
++ * Copyright 2007 Ralink Inc.
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of the GNU General Public License as published by the
++ * Free Software Foundation; either version 2 of the License, or (at your
++ * option) any later version.
++ *
++ * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
++ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
++ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
++ * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
++ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
++ * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
++ * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
++ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
++ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
++ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
++ *
++ * You should have received a copy of the GNU General Public License along
++ * with this program; if not, write to the Free Software Foundation, Inc.,
++ * 675 Mass Ave, Cambridge, MA 02139, USA.
++ *
++ *
++ **************************************************************************
++ */
++
++#ifndef __RALINK_MMAP__
++#define __RALINK_MMAP__
++
++#if defined (CONFIG_RALINK_RT2880_SHUTTLE)
++
++#define RALINK_SYSCTL_BASE 0xA0300000
++#define RALINK_TIMER_BASE 0xA0300100
++#define RALINK_INTCL_BASE 0xA0300200
++#define RALINK_MEMCTRL_BASE 0xA0300300
++#define RALINK_UART_BASE 0xA0300500
++#define RALINK_PIO_BASE 0xA0300600
++#define RALINK_I2C_BASE 0xA0300900
++#define RALINK_SPI_BASE 0xA0300B00
++#define RALINK_UART_LITE_BASE 0xA0300C00
++#define RALINK_FRAME_ENGINE_BASE 0xA0310000
++#define RALINK_EMBEDD_ROM_BASE 0xA0400000
++#define RALINK_PCI_BASE 0xA0500000
++#define RALINK_11N_MAC_BASE 0xA0600000
++
++//Interrupt Controller
++#define RALINK_INTCTL_TIMER0 (1<<0)
++#define RALINK_INTCTL_WDTIMER (1<<1)
++#define RALINK_INTCTL_UART (1<<2)
++#define RALINK_INTCTL_PIO (1<<3)
++#define RALINK_INTCTL_PCM (1<<4)
++#define RALINK_INTCTL_UARTLITE (1<<8)
++#define RALINK_INTCTL_ILL_ACCESS (1<<23)
++
++//Reset Control Register
++#define RALINK_TIMER_RST (1<<1)
++#define RALINK_INTC_RST (1<<2)
++#define RALINK_MC_RST (1<<3)
++#define RALINK_CPU_RST (1<<4)
++#define RALINK_UART_RST (1<<5)
++#define RALINK_PIO_RST (1<<6)
++#define RALINK_I2C_RST (1<<9)
++#define RALINK_SPI_RST (1<<11)
++#define RALINK_UART2_RST (1<<12)
++#define RALINK_PCI_RST (1<<16)
++#define RALINK_2860_RST (1<<17)
++#define RALINK_FE_RST (1<<18)
++#define RALINK_PCM_RST (1<<19)
++
++
++#elif defined (CONFIG_RALINK_RT2880_MP)
++
++#define RALINK_SYSCTL_BASE 0xA0300000
++#define RALINK_TIMER_BASE 0xA0300100
++#define RALINK_INTCL_BASE 0xA0300200
++#define RALINK_MEMCTRL_BASE 0xA0300300
++#define RALINK_UART_BASE 0xA0300500
++#define RALINK_PIO_BASE 0xA0300600
++#define RALINK_I2C_BASE 0xA0300900
++#define RALINK_SPI_BASE 0xA0300B00
++#define RALINK_UART_LITE_BASE 0x00300C00
++#define RALINK_FRAME_ENGINE_BASE 0xA0400000
++#define RALINK_EMBEDD_ROM_BASE 0xA0410000
++#define RALINK_PCI_BASE 0xA0440000
++#define RALINK_11N_MAC_BASE 0xA0480000
++
++//Interrupt Controller
++#define RALINK_INTCTL_TIMER0 (1<<0)
++#define RALINK_INTCTL_WDTIMER (1<<1)
++#define RALINK_INTCTL_UART (1<<2)
++#define RALINK_INTCTL_PIO (1<<3)
++#define RALINK_INTCTL_PCM (1<<4)
++#define RALINK_INTCTL_UARTLITE (1<<8)
++#define RALINK_INTCTL_ILL_ACCESS (1<<23)
++
++//Reset Control Register
++#define RALINK_TIMER_RST (1<<1)
++#define RALINK_INTC_RST (1<<2)
++#define RALINK_MC_RST (1<<3)
++#define RALINK_CPU_RST (1<<4)
++#define RALINK_UART_RST (1<<5)
++#define RALINK_PIO_RST (1<<6)
++#define RALINK_I2C_RST (1<<9)
++#define RALINK_SPI_RST (1<<11)
++#define RALINK_UART2_RST (1<<12)
++#define RALINK_PCI_RST (1<<16)
++#define RALINK_2860_RST (1<<17)
++#define RALINK_FE_RST (1<<18)
++#define RALINK_PCM_RST (1<<19)
++
++#elif defined (CONFIG_RALINK_RT3052)
++
++#define RALINK_SYSCTL_BASE 0xB0000000
++#define RALINK_TIMER_BASE 0xB0000100
++#define RALINK_INTCL_BASE 0xB0000200
++#define RALINK_MEMCTRL_BASE 0xB0000300
++#define RALINK_PCM_BASE 0xB0000400
++#define RALINK_UART_BASE 0x10000500
++#define RALINK_PIO_BASE 0xB0000600
++#define RALINK_GDMA_BASE 0xB0000700
++#define RALINK_NAND_CTRL_BASE 0xB0000800
++#define RALINK_I2C_BASE 0xB0000900
++#define RALINK_I2S_BASE 0xB0000A00
++#define RALINK_SPI_BASE 0xB0000B00
++#define RALINK_UART_LITE_BASE 0x10000C00
++#define RALINK_FRAME_ENGINE_BASE 0xB0100000
++#define RALINK_ETH_SW_BASE 0xB0110000
++#define RALINK_11N_MAC_BASE 0xB0180000
++#define RALINK_USB_OTG_BASE 0x101C0000
++
++//Interrupt Controller
++#define RALINK_INTCTL_SYSCTL (1<<0)
++#define RALINK_INTCTL_TIMER0 (1<<1)
++#define RALINK_INTCTL_WDTIMER (1<<2)
++#define RALINK_INTCTL_ILL_ACCESS (1<<3)
++#define RALINK_INTCTL_PCM (1<<4)
++#define RALINK_INTCTL_UART (1<<5)
++#define RALINK_INTCTL_PIO (1<<6)
++#define RALINK_INTCTL_DMA (1<<7)
++#define RALINK_INTCTL_NAND (1<<8)
++#define RALINK_INTCTL_PC (1<<9)
++#define RALINK_INTCTL_I2S (1<<10)
++#define RALINK_INTCTL_UARTLITE (1<<12)
++#define RALINK_INTCTL_ESW (1<<17)
++#define RALINK_INTCTL_OTG (1<<18)
++#define RALINK_INTCTL_OTG_IRQN 18
++#define RALINK_INTCTL_GLOBAL (1<<31)
++
++//Reset Control Register
++#define RALINK_SYS_RST (1<<0)
++#define RALINK_CPU_RST (1<<1)
++#define RALINK_TIMER_RST (1<<8)
++#define RALINK_INTC_RST (1<<9)
++#define RALINK_MC_RST (1<<10)
++#define RALINK_PCM_RST (1<<11)
++#define RALINK_UART_RST (1<<12)
++#define RALINK_PIO_RST (1<<13)
++#define RALINK_DMA_RST (1<<14)
++#define RALINK_I2C_RST (1<<16)
++#define RALINK_I2S_RST (1<<17)
++#define RALINK_SPI_RST (1<<18)
++#define RALINK_UARTL_RST (1<<19)
++#define RALINK_RT2872_RST (1<<20)
++#define RALINK_FE_RST (1<<21)
++#define RALINK_OTG_RST (1<<22)
++#define RALINK_SW_RST (1<<23)
++#define RALINK_EPHY_RST (1<<24)
++
++#elif defined (CONFIG_RALINK_RT3352)
++
++#define RALINK_SYSCTL_BASE 0xB0000000
++#define RALINK_TIMER_BASE 0xB0000100
++#define RALINK_INTCL_BASE 0xB0000200
++#define RALINK_MEMCTRL_BASE 0xB0000300
++#define RALINK_UART_BASE 0x10000500
++#define RALINK_PIO_BASE 0xB0000600
++#define RALINK_I2C_BASE 0xB0000900
++#define RALINK_I2S_BASE 0xB0000A00
++#define RALINK_SPI_BASE 0xB0000B00
++#define RALINK_NAND_CTRL_BASE 0xB0000800
++#define RALINK_UART_LITE_BASE 0x10000C00
++#define RALINK_PCM_BASE 0xB0002000
++#define RALINK_GDMA_BASE 0xB0002800
++#define RALINK_FRAME_ENGINE_BASE 0xB0100000
++#define RALINK_ETH_SW_BASE 0xB0110000
++#define RALINK_USB_DEV_BASE 0x10120000
++#define RALINK_11N_MAC_BASE 0xB0180000
++#define RALINK_USB_HOST_BASE 0x101C0000
++
++#define RALINK_MCNT_CFG 0xB0000D00
++#define RALINK_COMPARE 0xB0000D04
++#define RALINK_COUNT 0xB0000D08
++
++//Interrupt Controller
++#define RALINK_INTCTL_SYSCTL (1<<0)
++#define RALINK_INTCTL_TIMER0 (1<<1)
++#define RALINK_INTCTL_WDTIMER (1<<2)
++#define RALINK_INTCTL_ILL_ACCESS (1<<3)
++#define RALINK_INTCTL_PCM (1<<4)
++#define RALINK_INTCTL_UART (1<<5)
++#define RALINK_INTCTL_PIO (1<<6)
++#define RALINK_INTCTL_DMA (1<<7)
++#define RALINK_INTCTL_PC (1<<9)
++#define RALINK_INTCTL_I2S (1<<10)
++#define RALINK_INTCTL_UARTLITE (1<<12)
++#define RALINK_INTCTL_ESW (1<<17)
++#define RALINK_INTCTL_OTG (1<<18)
++#define RALINK_INTCTL_GLOBAL (1<<31)
++
++//Reset Control Register
++#define RALINK_SYS_RST (1<<0)
++#define RALINK_TIMER_RST (1<<8)
++#define RALINK_INTC_RST (1<<9)
++#define RALINK_MC_RST (1<<10)
++#define RALINK_PCM_RST (1<<11)
++#define RALINK_UART_RST (1<<12)
++#define RALINK_PIO_RST (1<<13)
++#define RALINK_DMA_RST (1<<14)
++#define RALINK_I2C_RST (1<<16)
++#define RALINK_I2S_RST (1<<17)
++#define RALINK_SPI_RST (1<<18)
++#define RALINK_UARTL_RST (1<<19)
++#define RALINK_WLAN_RST (1<<20)
++#define RALINK_FE_RST (1<<21)
++#define RALINK_UHST_RST (1<<22)
++#define RALINK_ESW_RST (1<<23)
++#define RALINK_EPHY_RST (1<<24)
++#define RALINK_UDEV_RST (1<<25)
++
++
++//Clock Conf Register
++#define RALINK_UPHY1_CLK_EN (1<<20)
++#define RALINK_UPHY0_CLK_EN (1<<18)
++#define RALINK_GE1_CLK_EN (1<<16)
++
++
++#elif defined (CONFIG_RALINK_RT5350)
++
++#define RALINK_SYSCTL_BASE 0xB0000000
++#define RALINK_TIMER_BASE 0xB0000100
++#define RALINK_INTCL_BASE 0xB0000200
++#define RALINK_MEMCTRL_BASE 0xB0000300
++#define RALINK_UART_BASE 0x10000500
++#define RALINK_PIO_BASE 0xB0000600
++#define RALINK_I2C_BASE 0xB0000900
++#define RALINK_I2S_BASE 0xB0000A00
++#define RALINK_SPI_BASE 0xB0000B00
++#define RALINK_UART_LITE_BASE 0x10000C00
++#define RALINK_PCM_BASE 0xB0002000
++#define RALINK_GDMA_BASE 0xB0002800
++#define RALINK_FRAME_ENGINE_BASE 0xB0100000
++#define RALINK_ETH_SW_BASE 0xB0110000
++#define RALINK_USB_DEV_BASE 0x10120000
++#define RALINK_11N_MAC_BASE 0xB0180000
++#define RALINK_USB_HOST_BASE 0x101C0000
++
++#define RALINK_MCNT_CFG 0xB0000D00
++#define RALINK_COMPARE 0xB0000D04
++#define RALINK_COUNT 0xB0000D08
++
++//Interrupt Controller
++#define RALINK_INTCTL_SYSCTL (1<<0)
++#define RALINK_INTCTL_TIMER0 (1<<1)
++#define RALINK_INTCTL_WDTIMER (1<<2)
++#define RALINK_INTCTL_ILL_ACCESS (1<<3)
++#define RALINK_INTCTL_PCM (1<<4)
++#define RALINK_INTCTL_UART (1<<5)
++#define RALINK_INTCTL_PIO (1<<6)
++#define RALINK_INTCTL_DMA (1<<7)
++#define RALINK_INTCTL_PC (1<<9)
++#define RALINK_INTCTL_I2S (1<<10)
++#define RALINK_INTCTL_UARTLITE (1<<12)
++#define RALINK_INTCTL_ESW (1<<17)
++#define RALINK_INTCTL_USB_HOST (1<<18)
++#define RALINK_INTCTL_USB_DEV (1<<19)
++#define RALINK_INTCTL_GLOBAL (1<<31)
++
++//Reset Control Register
++#define RALINK_SYS_RST (1<<0)
++#define RALINK_TIMER_RST (1<<8)
++#define RALINK_INTC_RST (1<<9)
++#define RALINK_MC_RST (1<<10)
++#define RALINK_PCM_RST (1<<11)
++#define RALINK_UART_RST (1<<12)
++#define RALINK_PIO_RST (1<<13)
++#define RALINK_DMA_RST (1<<14)
++#define RALINK_I2C_RST (1<<16)
++#define RALINK_I2S_RST (1<<17)
++#define RALINK_SPI_RST (1<<18)
++#define RALINK_UARTL_RST (1<<19)
++#define RALINK_WLAN_RST (1<<20)
++#define RALINK_FE_RST (1<<21)
++#define RALINK_UHST_RST (1<<22)
++#define RALINK_ESW_RST (1<<23)
++#define RALINK_EPHY_RST (1<<24)
++#define RALINK_UDEV_RST (1<<25)
++#define RALINK_MIPSC_RST (1<<28)
++
++//Clock Conf Register
++#define RALINK_UPHY0_CLK_EN (1<<18)
++#define RALINK_GE1_CLK_EN (1<<16)
++
++#elif defined (CONFIG_RALINK_RT2883)
++
++#define RALINK_SYSCTL_BASE 0xB0000000
++#define RALINK_TIMER_BASE 0xB0000100
++#define RALINK_INTCL_BASE 0xB0000200
++#define RALINK_MEMCTRL_BASE 0xB0000300
++#define RALINK_PCM_BASE 0xB0000400
++#define RALINK_UART_BASE 0x10000500
++#define RALINK_PIO_BASE 0xB0000600
++#define RALINK_GDMA_BASE 0xB0000700
++#define RALINK_NAND_CTRL_BASE 0xB0000800
++#define RALINK_I2C_BASE 0xB0000900
++#define RALINK_I2S_BASE 0xB0000A00
++#define RALINK_SPI_BASE 0xB0000B00
++#define RALINK_UART_LITE_BASE 0x10000C00
++#define RALINK_FRAME_ENGINE_BASE 0xB0100000
++#define RALINK_PCI_BASE 0xB0140000
++#define RALINK_11N_MAC_BASE 0xB0180000
++#define RALINK_USB_OTG_BASE 0x101C0000
++
++//Interrupt Controller
++#define RALINK_INTCTL_SYSCTL (1<<0)
++#define RALINK_INTCTL_TIMER0 (1<<1)
++#define RALINK_INTCTL_WDTIMER (1<<2)
++#define RALINK_INTCTL_ILL_ACCESS (1<<3)
++#define RALINK_INTCTL_PCM (1<<4)
++#define RALINK_INTCTL_UART (1<<5)
++#define RALINK_INTCTL_PIO (1<<6)
++#define RALINK_INTCTL_DMA (1<<7)
++#define RALINK_INTCTL_NAND (1<<8)
++#define RALINK_INTCTL_PC (1<<9)
++#define RALINK_INTCTL_I2S (1<<10)
++#define RALINK_INTCTL_UARTLITE (1<<12)
++#define RALINK_INTCTL_OTG (1<<18)
++#define RALINK_INTCTL_OTG_IRQN 18
++#define RALINK_INTCTL_GLOBAL (1<<31)
++
++//Reset Control Register
++#define RALINK_SYS_RST (1<<0)
++#define RALINK_CPU_RST (1<<1)
++#define RALINK_TIMER_RST (1<<8)
++#define RALINK_INTC_RST (1<<9)
++#define RALINK_MC_RST (1<<10)
++#define RALINK_PCM_RST (1<<11)
++#define RALINK_UART_RST (1<<12)
++#define RALINK_PIO_RST (1<<13)
++#define RALINK_DMA_RST (1<<14)
++#define RALINK_I2C_RST (1<<16)
++#define RALINK_I2S_RST (1<<17)
++#define RALINK_SPI_RST (1<<18)
++#define RALINK_UARTL_RST (1<<19)
++#define RALINK_WLAN_RST (1<<20)
++#define RALINK_FE_RST (1<<21)
++#define RALINK_OTG_RST (1<<22)
++#define RALINK_PCIE_RST (1<<23)
++
++#elif defined (CONFIG_RALINK_RT3883)
++
++#define RALINK_SYSCTL_BASE 0xB0000000
++#define RALINK_TIMER_BASE 0xB0000100
++#define RALINK_INTCL_BASE 0xB0000200
++#define RALINK_MEMCTRL_BASE 0xB0000300
++#define RALINK_UART_BASE 0x10000500
++#define RALINK_PIO_BASE 0xB0000600
++#define RALINK_NOR_CTRL_BASE 0xB0000700
++#define RALINK_NAND_CTRL_BASE 0xB0000810
++#define RALINK_I2C_BASE 0xB0000900
++#define RALINK_I2S_BASE 0xB0000A00
++#define RALINK_SPI_BASE 0xB0000B00
++#define RALINK_UART_LITE_BASE 0x10000C00
++#define RALINK_PCM_BASE 0xB0002000
++#define RALINK_GDMA_BASE 0xB0002800
++#define RALINK_CODEC1_BASE 0xB0003000
++#define RALINK_CODEC2_BASE 0xB0003800
++#define RALINK_FRAME_ENGINE_BASE 0xB0100000
++#define RALINK_USB_DEV_BASE 0x10120000
++#define RALINK_PCI_BASE 0xB0140000
++#define RALINK_11N_MAC_BASE 0xB0180000
++#define RALINK_USB_HOST_BASE 0x101C0000
++#define RALINK_PCIE_BASE 0xB0200000
++
++//Interrupt Controller
++#define RALINK_INTCTL_SYSCTL (1<<0)
++#define RALINK_INTCTL_TIMER0 (1<<1)
++#define RALINK_INTCTL_WDTIMER (1<<2)
++#define RALINK_INTCTL_ILL_ACCESS (1<<3)
++#define RALINK_INTCTL_PCM (1<<4)
++#define RALINK_INTCTL_UART (1<<5)
++#define RALINK_INTCTL_PIO (1<<6)
++#define RALINK_INTCTL_DMA (1<<7)
++#define RALINK_INTCTL_NAND (1<<8)
++#define RALINK_INTCTL_PC (1<<9)
++#define RALINK_INTCTL_I2S (1<<10)
++#define RALINK_INTCTL_UARTLITE (1<<12)
++#define RALINK_INTCTL_UHST (1<<18)
++#define RALINK_INTCTL_UDEV (1<<19)
++
++//Reset Control Register
++#define RALINK_SYS_RST (1<<0)
++#define RALINK_TIMER_RST (1<<8)
++#define RALINK_INTC_RST (1<<9)
++#define RALINK_MC_RST (1<<10)
++#define RALINK_PCM_RST (1<<11)
++#define RALINK_UART_RST (1<<12)
++#define RALINK_PIO_RST (1<<13)
++#define RALINK_DMA_RST (1<<14)
++#define RALINK_NAND_RST (1<<15)
++#define RALINK_I2C_RST (1<<16)
++#define RALINK_I2S_RST (1<<17)
++#define RALINK_SPI_RST (1<<18)
++#define RALINK_UARTL_RST (1<<19)
++#define RALINK_WLAN_RST (1<<20)
++#define RALINK_FE_RST (1<<21)
++#define RALINK_UHST_RST (1<<22)
++#define RALINK_PCIE_RST (1<<23)
++#define RALINK_PCI_RST (1<<24)
++#define RALINK_UDEV_RST (1<<25)
++#define RALINK_FLASH_RST (1<<26)
++
++//Clock Conf Register
++#define RALINK_UPHY1_CLK_EN (1<<20)
++#define RALINK_UPHY0_CLK_EN (1<<18)
++#define RALINK_GE1_CLK_EN (1<<16)
++
++#elif defined (CONFIG_RALINK_RT6855)
++
++#define RALINK_SYSCTL_BASE 0xB0000000
++#define RALINK_TIMER_BASE 0xB0000100
++#define RALINK_INTCL_BASE 0xB0000200
++#define RALINK_MEMCTRL_BASE 0xB0000300
++#define RALINK_UART_BASE 0x10000500
++#define RALINK_PIO_BASE 0xB0000600
++#define RALINK_I2C_BASE 0xB0000900
++#define RALINK_I2S_BASE 0xB0000A00
++#define RALINK_SPI_BASE 0xB0000B00
++#define RALINK_NAND_CTRL_BASE 0xB0000800
++#define RALINK_UART_LITE_BASE 0x10000C00
++#define RALINK_PCM_BASE 0xB0002000
++#define RALINK_GDMA_BASE 0xB0002800
++#define RALINK_FRAME_ENGINE_BASE 0xB0100000
++#define RALINK_ETH_SW_BASE 0xB0110000
++#define RALINK_PCI_BASE 0xB0140000
++#define RALINK_USB_DEV_BASE 0x10120000
++#define RALINK_11N_MAC_BASE 0x00000000
++#define RALINK_USB_HOST_BASE 0x101C0000
++
++#define RALINK_MCNT_CFG 0xB0000D00
++#define RALINK_COMPARE 0xB0000D04
++#define RALINK_COUNT 0xB0000D08
++
++//Interrupt Controller
++#define RALINK_INTCTL_SYSCTL (1<<0)
++#define RALINK_INTCTL_TIMER0 (1<<1)
++#define RALINK_INTCTL_WDTIMER (1<<2)
++#define RALINK_INTCTL_ILL_ACCESS (1<<3)
++#define RALINK_INTCTL_PCM (1<<4)
++#define RALINK_INTCTL_UART (1<<5)
++#define RALINK_INTCTL_PIO (1<<6)
++#define RALINK_INTCTL_DMA (1<<7)
++#define RALINK_INTCTL_PC (1<<9)
++#define RALINK_INTCTL_I2S (1<<10)
++#define RALINK_INTCTL_UARTLITE (1<<12)
++#define RALINK_INTCTL_ESW (1<<17)
++#define RALINK_INTCTL_OTG (1<<18)
++#define RALINK_INTCTL_GLOBAL (1<<31)
++
++//Reset Control Register
++#define RALINK_SYS_RST (1<<0)
++#define RALINK_TIMER_RST (1<<8)
++#define RALINK_INTC_RST (1<<9)
++#define RALINK_MC_RST (1<<10)
++#define RALINK_PCM_RST (1<<11)
++#define RALINK_UART_RST (1<<12)
++#define RALINK_PIO_RST (1<<13)
++#define RALINK_DMA_RST (1<<14)
++#define RALINK_I2C_RST (1<<16)
++#define RALINK_I2S_RST (1<<17)
++#define RALINK_SPI_RST (1<<18)
++#define RALINK_UARTL_RST (1<<19)
++#define RALINK_FE_RST (1<<21)
++#define RALINK_UHST_RST (1<<22)
++#define RALINK_ESW_RST (1<<23)
++#define RALINK_EPHY_RST (1<<24)
++#define RALINK_UDEV_RST (1<<25)
++#define RALINK_PCIE0_RST (1<<26)
++#define RALINK_PCIE1_RST (1<<27)
++
++//Clock Conf Register
++#define RALINK_UPHY0_CLK_EN (1<<25)
++#define RALINK_PCIE0_CLK_EN (1<<26)
++#define RALINK_PCIE1_CLK_EN (1<<27)
++
++
++#elif defined (CONFIG_RALINK_RT6855A)
++
++#define RALINK_SYSCTL_BASE 0xBFB00000
++#define RALINK_TIMER_BASE 0xBFBF0100
++#define RALINK_INTCL_BASE 0xBFB40000
++#define RALINK_MEMCTRL_BASE 0xBFB20000
++#define RALINK_PIO_BASE 0xBFBF0200
++#define RALINK_NAND_CTRL_BASE 0xBFBE0010
++#define RALINK_I2C_BASE 0xBFBF8000
++#define RALINK_I2S_BASE 0xBFBF8100
++#define RALINK_SPI_BASE 0xBFBC0B00
++#define RALINK_UART_LITE_BASE 0xBFBF0000
++#define RALINK_UART_LITE2_BASE 0xBFBF0300
++#define RALINK_PCM_BASE 0xBFBD0000
++#define RALINK_GDMA_BASE 0xBFB30000
++#define RALINK_FRAME_ENGINE_BASE 0xBFB50000
++#define RALINK_ETH_SW_BASE 0xBFB58000
++#define RALINK_11N_MAC_BASE 0x00000000
++//#define RALINK_USB_DEV_BASE 0xB0120000
++#define RALINK_CRYPTO_ENGINE_BASE 0xBFB70000
++#define RALINK_PCI_BASE 0xBFB80000
++//#define RALINK_USB_HOST_BASE 0xB01C0000
++#define RALINK_PCIE_BASE 0xBFB81000
++
++//Interrupt Controller
++#define RALINK_INTCTL_UARTLITE (1<<0)
++#define RALINK_INTCTL_PIO (1<<10)
++#define RALINK_INTCTL_PCM (1<<11)
++#define RALINK_INTCTL_DMA (1<<14)
++#define RALINK_INTCTL_GMAC2 (1<<15)
++#define RALINK_INTCTL_PCI (1<<17)
++#define RALINK_INTCTL_UHST2 (1<<20)
++#define RALINK_INTCTL_GMAC1 (1<<21)
++#define RALINK_INTCTL_UHST1 (1<<23)
++#define RALINK_INTCTL_PCIE (1<<24)
++#define RALINK_INTCTL_NAND (1<<25)
++#define RALINK_INTCTL_SPI (1<<27)
++
++//Reset Control Register
++#define RALINK_PCM_RST (1<<11)
++#define RALINK_DMA_RST (1<<14)
++#define RALINK_I2C_RST (1<<16)
++#define RALINK_I2S_RST (1<<2) /* IMR1 */
++
++//Clock Conf Register
++#define RALINK_UPHY0_CLK_EN (1<<25)
++#define RALINK_PCIE0_CLK_EN (1<<26)
++#define RALINK_PCIE1_CLK_EN (1<<27)
++
++#endif
++#endif
+diff --git a/drivers/char/Makefile b/drivers/char/Makefile
+index 7c5ea6f9df14..d5d21e6705fc 100644
+--- a/drivers/char/Makefile
++++ b/drivers/char/Makefile
+@@ -3,6 +3,7 @@
+ # Makefile for the kernel character device drivers.
+ #
+
++#obj-y += ralink_gdma.o
+ obj-y += mem.o random.o
+ obj-$(CONFIG_TTY_PRINTK) += ttyprintk.o
+ obj-y += misc.o
+diff --git a/drivers/net/wireless/ralink/rt2x00/rt2800pci.c b/drivers/net/wireless/ralink/rt2x00/rt2800pci.c
+index a23c26574002..99c2bb277942 100644
+--- a/drivers/net/wireless/ralink/rt2x00/rt2800pci.c
++++ b/drivers/net/wireless/ralink/rt2x00/rt2800pci.c
+@@ -283,6 +283,57 @@ static int rt2800pci_read_eeprom(struct rt2x00_dev *rt2x00dev)
+ else
+ retval = rt2800pci_read_eeprom_pci(rt2x00dev);
+
++static u8 eeprom_wifi[] = {
++ 0x92, 0x55, 0x07, 0x01, 0x58, 0xef, 0x68, 0xc7, 0x51, 0xbc, 0x92, 0x55,
++ 0x14, 0x18, 0x01, 0x80, 0x00, 0x00, 0x92, 0x55, 0x14, 0x18, 0x00, 0x00,
++ 0x01, 0x00, 0x6a, 0xff, 0x13, 0x02, 0xff, 0xff, 0xff, 0xff, 0xc1, 0xff,
++ 0x01, 0x92, 0xff, 0xff, 0x00, 0x72, 0x22, 0xe0, 0x00, 0x46, 0x00, 0x21,
++ 0xd4, 0x20, 0x00, 0x70, 0x22, 0xff, 0x27, 0x00, 0x06, 0x01, 0x0f, 0x01,
++ 0xff, 0xff, 0x00, 0x22, 0xcc, 0x88, 0xff, 0xff, 0x08, 0x07, 0x00, 0x00,
++ 0x00, 0x07, 0x00, 0x00, 0x00, 0x07, 0xff, 0xff, 0xff, 0x00, 0x14, 0x14,
++ 0x15, 0x16, 0x16, 0x17, 0x18, 0x17, 0x16, 0x16, 0x15, 0x14, 0x14, 0x14,
++ 0x0c, 0x0c, 0x0d, 0x0e, 0x0f, 0x10, 0x11, 0x10, 0x0f, 0x0f, 0x0e, 0x0d,
++ 0x0d, 0x0d, 0x42, 0x73, 0xf7, 0x00, 0x86, 0x0f, 0x00, 0x00, 0x72, 0xe6,
++ 0x0f, 0x0e, 0x0e, 0x0e, 0x0e, 0x0e, 0x0e, 0x0e, 0x0e, 0x0e, 0x0e, 0x0f,
++ 0x0f, 0x0f, 0x0f, 0x0f, 0x0f, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x11,
++ 0x11, 0x11, 0x11, 0x11, 0x12, 0x12, 0x12, 0x13, 0x13, 0x14, 0x14, 0x14,
++ 0x14, 0x14, 0x14, 0x00, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x10, 0x0f,
++ 0x0f, 0x0f, 0x0f, 0x0f, 0x0f, 0x0f, 0x0f, 0x0f, 0x0f, 0x0f, 0x0f, 0x0f,
++ 0x0f, 0x0f, 0x0f, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10,
++ 0x10, 0x10, 0x11, 0x11, 0x12, 0x13, 0x14, 0x15, 0x15, 0x15, 0x15, 0x15,
++ 0x15, 0x00, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x43, 0x43, 0xf3, 0x00,
++ 0x21, 0xfa, 0x00, 0x00, 0x72, 0xe6, 0x33, 0x33, 0x66, 0x66, 0x66, 0x66,
++ 0x66, 0x66, 0x66, 0x55, 0x66, 0x66, 0x66, 0x55, 0x66, 0x66, 0x66, 0x66,
++ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
++ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
++ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
++ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
++ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
++ 0xff, 0xff, 0xff, 0xff, 0x3f, 0x03, 0xff, 0x3e, 0x01, 0xff, 0xff, 0xff,
++ 0xff, 0xff, 0xff, 0xff, 0x0c, 0x60, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
++ 0x02, 0x00, 0x03, 0x3c, 0x02, 0x3c, 0x02, 0x3e, 0x02, 0x3b, 0x00, 0x3a,
++ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
++ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
++ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
++ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
++ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
++ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
++ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
++ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
++ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
++ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
++ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x01, 0x30, 0x74, 0x31,
++ 0x32, 0x58, 0x31, 0x30, 0x50, 0x30, 0x43, 0x37, 0x30, 0x31, 0x37, 0x37,
++ 0x38, 0xff, 0x31, 0xff, 0x00, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
++ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
++ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff
++};
++
++ memcpy(rt2x00dev->eeprom, eeprom_wifi, sizeof(eeprom_wifi));
++
++ if (0) print_hex_dump(KERN_INFO, "", DUMP_PREFIX_ADDRESS, 32,
++ 4, rt2x00dev->eeprom, 512, 0);
++
+ return retval;
+ }
+
+diff --git a/drivers/spi/spi-mt7621.c b/drivers/spi/spi-mt7621.c
+index 2c3b7a2a1ec7..6091207b4370 100644
+--- a/drivers/spi/spi-mt7621.c
++++ b/drivers/spi/spi-mt7621.c
+@@ -87,7 +87,7 @@ static void mt7621_spi_set_cs(struct spi_device *spi, int enable)
+ * reliably)
+ */
+ master = mt7621_spi_read(rs, MT7621_SPI_MASTER);
+- master |= MASTER_RS_SLAVE_SEL | MASTER_MORE_BUFMODE;
++ master |= /*MASTER_RS_SLAVE_SEL |*/ MASTER_MORE_BUFMODE;
+ master &= ~MASTER_FULL_DUPLEX;
+ mt7621_spi_write(rs, MT7621_SPI_MASTER, master);
+
+@@ -338,7 +338,7 @@ static int mt7621_spi_probe(struct platform_device *pdev)
+ base = devm_platform_ioremap_resource(pdev, 0);
+ if (IS_ERR(base))
+ return PTR_ERR(base);
+-
++#if 0
+ clk = devm_clk_get(&pdev->dev, NULL);
+ if (IS_ERR(clk)) {
+ dev_err(&pdev->dev, "unable to get SYS clock, err=%d\n",
+@@ -349,7 +349,7 @@ static int mt7621_spi_probe(struct platform_device *pdev)
+ status = clk_prepare_enable(clk);
+ if (status)
+ return status;
+-
++#endif
+ master = spi_alloc_master(&pdev->dev, sizeof(*rs));
+ if (!master) {
+ dev_info(&pdev->dev, "master allocation failed\n");
+@@ -370,16 +370,16 @@ static int mt7621_spi_probe(struct platform_device *pdev)
+ rs->base = base;
+ rs->clk = clk;
+ rs->master = master;
+- rs->sys_freq = clk_get_rate(rs->clk);
++ rs->sys_freq = 233333333;//clk_get_rate(rs->clk);
+ rs->pending_write = 0;
+ dev_info(&pdev->dev, "sys_freq: %u\n", rs->sys_freq);
+
+- ret = device_reset(&pdev->dev);
++/* ret = device_reset(&pdev->dev);
+ if (ret) {
+ dev_err(&pdev->dev, "SPI reset failed!\n");
+ return ret;
+ }
+-
++*/
+ return devm_spi_register_controller(&pdev->dev, master);
+ }
+
+@@ -391,7 +391,7 @@ static int mt7621_spi_remove(struct platform_device *pdev)
+ master = dev_get_drvdata(&pdev->dev);
+ rs = spi_controller_get_devdata(master);
+
+- clk_disable_unprepare(rs->clk);
++// clk_disable_unprepare(rs->clk);
+
+ return 0;
+ }
+diff --git a/drivers/watchdog/Kconfig b/drivers/watchdog/Kconfig
+index 58e7c100b6ad..c0d8594472ff 100644
+--- a/drivers/watchdog/Kconfig
++++ b/drivers/watchdog/Kconfig
+@@ -1795,6 +1795,13 @@ config RALINK_WDT
+ help
+ Hardware driver for the Ralink SoC Watchdog Timer.
+
++config RT6855_WDT
++ tristate "Ralink RT6855 SoC watchdog"
++ select WATCHDOG_CORE
++ depends on RALINK
++ help
++ Hardware driver for the Ralink RT6855 SoC Watchdog Timer.
++
+ config MT7621_WDT
+ tristate "Mediatek SoC watchdog"
+ select WATCHDOG_CORE
+diff --git a/drivers/watchdog/Makefile b/drivers/watchdog/Makefile
+index 2ee352bf3372..4522c5466a8c 100644
+--- a/drivers/watchdog/Makefile
++++ b/drivers/watchdog/Makefile
+@@ -167,6 +167,7 @@ octeon-wdt-y := octeon-wdt-main.o octeon-wdt-nmi.o
+ obj-$(CONFIG_LANTIQ_WDT) += lantiq_wdt.o
+ obj-$(CONFIG_LOONGSON1_WDT) += loongson1_wdt.o
+ obj-$(CONFIG_RALINK_WDT) += rt2880_wdt.o
++obj-$(CONFIG_RT6855_WDT) += rt6855_wdt.o
+ obj-$(CONFIG_IMGPDC_WDT) += imgpdc_wdt.o
+ obj-$(CONFIG_MT7621_WDT) += mt7621_wdt.o
+ obj-$(CONFIG_PIC32_WDT) += pic32-wdt.o
+diff --git a/drivers/watchdog/rt6855_wdt.c b/drivers/watchdog/rt6855_wdt.c
+new file mode 100644
+index 000000000000..0fe773b3c536
+--- /dev/null
++++ b/drivers/watchdog/rt6855_wdt.c
+@@ -0,0 +1,177 @@
++// SPDX-License-Identifier: GPL-2.0-only
++/*
++ * Ralink RT6855 built-in hardware watchdog timer
++ *
++ * Copyright (C) 2014 John Crispin <john at phrozen.org>
++ *
++ * This driver was based on: drivers/watchdog/rt6855_wdt.c
++ */
++
++#include <linux/clk.h>
++#include <linux/reset.h>
++#include <linux/module.h>
++#include <linux/kernel.h>
++#include <linux/watchdog.h>
++#include <linux/moduleparam.h>
++#include <linux/platform_device.h>
++#include <linux/mod_devicetable.h>
++
++#include <asm/mach-ralink/ralink_regs.h>
++
++#define TIMER_REG_TMRSTAT 0x38
++#define TIMER_REG_TMR1LOAD 0x2C
++#define TIMER_REG_TMR1CTL 0x00
++
++#define TMR1CTL_ENABLE (BIT(5)|BIT(25))
++#define TMR1CTL_RESTART BIT(0)
++
++static void __iomem *rt6855_wdt_base;
++static struct reset_control *rt6855_wdt_reset;
++
++static bool nowayout = WATCHDOG_NOWAYOUT;
++module_param(nowayout, bool, 0);
++MODULE_PARM_DESC(nowayout,
++ "Watchdog cannot be stopped once started (default="
++ __MODULE_STRING(WATCHDOG_NOWAYOUT) ")");
++
++static inline void rt_wdt_w32(unsigned reg, u32 val)
++{
++ iowrite32(val, rt6855_wdt_base + reg);
++}
++
++static inline u32 rt_wdt_r32(unsigned reg)
++{
++ return ioread32(rt6855_wdt_base + reg);
++}
++
++static int rt6855_wdt_ping(struct watchdog_device *w)
++{
++ rt_wdt_w32(TIMER_REG_TMRSTAT, TMR1CTL_RESTART);
++
++ return 0;
++}
++
++static int rt6855_wdt_set_timeout(struct watchdog_device *w, unsigned int t)
++{
++ w->timeout = t;
++ rt_wdt_w32(TIMER_REG_TMR1LOAD, t * 1000 * (23333/100)*1000/2);
++ rt6855_wdt_ping(w);
++
++ return 0;
++}
++
++static int rt6855_wdt_start(struct watchdog_device *w)
++{
++ u32 t;
++
++ rt6855_wdt_set_timeout(w, w->timeout);
++
++ t = rt_wdt_r32(TIMER_REG_TMR1CTL);
++ t |= TMR1CTL_ENABLE;
++ rt_wdt_w32(TIMER_REG_TMR1CTL, t);
++
++ return 0;
++}
++
++static int rt6855_wdt_stop(struct watchdog_device *w)
++{
++ u32 t;
++
++ rt6855_wdt_ping(w);
++
++ t = rt_wdt_r32(TIMER_REG_TMR1CTL);
++ t &= ~TMR1CTL_ENABLE;
++ rt_wdt_w32(TIMER_REG_TMR1CTL, t);
++
++ return 0;
++}
++
++static int rt6855_wdt_bootcause(void)
++{
++ return 0;
++}
++
++static int rt6855_wdt_is_running(struct watchdog_device *w)
++{
++ return !!(rt_wdt_r32(TIMER_REG_TMR1CTL) & TMR1CTL_ENABLE);
++}
++
++static const struct watchdog_info rt6855_wdt_info = {
++ .identity = "Ralink Watchdog",
++ .options = WDIOF_SETTIMEOUT | WDIOF_KEEPALIVEPING | WDIOF_MAGICCLOSE,
++};
++
++static const struct watchdog_ops rt6855_wdt_ops = {
++ .owner = THIS_MODULE,
++ .start = rt6855_wdt_start,
++ .stop = rt6855_wdt_stop,
++ .ping = rt6855_wdt_ping,
++ .set_timeout = rt6855_wdt_set_timeout,
++};
++
++static struct watchdog_device rt6855_wdt_dev = {
++ .info = &rt6855_wdt_info,
++ .ops = &rt6855_wdt_ops,
++ .min_timeout = 1,
++ .max_timeout = 0xfffffffful / (1000*23333/100*1000/2),
++};
++
++static int rt6855_wdt_probe(struct platform_device *pdev)
++{
++ struct device *dev = &pdev->dev;
++ rt6855_wdt_base = devm_platform_ioremap_resource(pdev, 0);
++ if (IS_ERR(rt6855_wdt_base))
++ return PTR_ERR(rt6855_wdt_base);
++
++ rt6855_wdt_reset = devm_reset_control_get_exclusive(dev, NULL);
++ if (!IS_ERR(rt6855_wdt_reset))
++ reset_control_deassert(rt6855_wdt_reset);
++
++ rt6855_wdt_dev.bootstatus = rt6855_wdt_bootcause();
++
++ watchdog_init_timeout(&rt6855_wdt_dev, rt6855_wdt_dev.max_timeout,
++ dev);
++ watchdog_set_nowayout(&rt6855_wdt_dev, nowayout);
++ if (rt6855_wdt_is_running(&rt6855_wdt_dev)) {
++ /*
++ * Make sure to apply timeout from watchdog core, taking
++ * the prescaler of this driver here into account (the
++ * boot loader might be using a different prescaler).
++ *
++ * To avoid spurious resets because of different scaling,
++ * we first disable the watchdog, set the new prescaler
++ * and timeout, and then re-enable the watchdog.
++ */
++ rt6855_wdt_stop(&rt6855_wdt_dev);
++ rt6855_wdt_start(&rt6855_wdt_dev);
++ set_bit(WDOG_HW_RUNNING, &rt6855_wdt_dev.status);
++ }
++
++ return devm_watchdog_register_device(dev, &rt6855_wdt_dev);
++}
++
++static void rt6855_wdt_shutdown(struct platform_device *pdev)
++{
++ rt6855_wdt_stop(&rt6855_wdt_dev);
++}
++
++static const struct of_device_id rt6855_wdt_match[] = {
++ { .compatible = "ralink,rt6855-wdt" },
++ {},
++};
++MODULE_DEVICE_TABLE(of, rt6855_wdt_match);
++
++static struct platform_driver rt6855_wdt_driver = {
++ .probe = rt6855_wdt_probe,
++ .shutdown = rt6855_wdt_shutdown,
++ .driver = {
++ .name = KBUILD_MODNAME,
++ .of_match_table = rt6855_wdt_match,
++ },
++};
++
++module_platform_driver(rt6855_wdt_driver);
++
++MODULE_DESCRIPTION("Ralink RT6855 hardware watchdog driver");
++MODULE_AUTHOR("John Crispin <john at phrozen.org");
++MODULE_LICENSE("GPL v2");
+diff --git a/kernel/dma/direct.c b/kernel/dma/direct.c
+index 8402b29c280f..da61fdda48e7 100644
+--- a/kernel/dma/direct.c
++++ b/kernel/dma/direct.c
+@@ -78,6 +78,7 @@ static gfp_t __dma_direct_optimal_gfp_mask(struct device *dev, u64 dma_mask,
+
+ static bool dma_coherent_ok(struct device *dev, phys_addr_t phys, size_t size)
+ {
++ return true;
+ return phys_to_dma_direct(dev, phys) + size - 1 <=
+ min_not_zero(dev->coherent_dma_mask, dev->bus_dma_mask);
+ }
+diff --git a/scripts/Makefile b/scripts/Makefile
+index 3e86b300f5a1..8dad78e09808 100644
+--- a/scripts/Makefile
++++ b/scripts/Makefile
+@@ -23,8 +23,8 @@ hostprogs-$(CONFIG_SYSTEM_EXTRA_CERTIFICATE) += insert-sys-cert
+
+ HOSTCFLAGS_sortextable.o = -I$(srctree)/tools/include
+ HOSTCFLAGS_asn1_compiler.o = -I$(srctree)/include
+-HOSTLDLIBS_sign-file = -lcrypto
+-HOSTLDLIBS_extract-cert = -lcrypto
++HOSTLDLIBS_sign-file = -lcrypto -lpthread
++HOSTLDLIBS_extract-cert = -lcrypto -lpthread
+
+ always := $(hostprogs-y) $(hostprogs-m)
+
+--
+2.27.0
+
diff --git a/target/linux/ramips/rt6855a/base-files/etc/board.d/01_leds b/target/linux/ramips/rt6855a/base-files/etc/board.d/01_leds
new file mode 100755
index 0000000000..b3acaa5410
--- /dev/null
+++ b/target/linux/ramips/rt6855a/base-files/etc/board.d/01_leds
@@ -0,0 +1,12 @@
+#!/bin/sh
+
+. /lib/functions/leds.sh
+. /lib/functions/uci-defaults.sh
+
+board=$(board_name)
+
+board_config_update
+
+board_config_flush
+
+exit 0
diff --git a/target/linux/ramips/rt6855a/base-files/etc/board.d/02_network b/target/linux/ramips/rt6855a/base-files/etc/board.d/02_network
new file mode 100755
index 0000000000..af223209c8
--- /dev/null
+++ b/target/linux/ramips/rt6855a/base-files/etc/board.d/02_network
@@ -0,0 +1,11 @@
+#!/bin/sh
+
+. /lib/functions.sh
+. /lib/functions/uci-defaults.sh
+. /lib/functions/system.sh
+
+board_config_update
+ucidef_set_interface_lan "eth0"
+board_config_flush
+
+exit 0
diff --git a/target/linux/ramips/rt6855a/base-files/etc/board.d/03_gpio_switches b/target/linux/ramips/rt6855a/base-files/etc/board.d/03_gpio_switches
new file mode 100755
index 0000000000..69a5f27a95
--- /dev/null
+++ b/target/linux/ramips/rt6855a/base-files/etc/board.d/03_gpio_switches
@@ -0,0 +1,11 @@
+#!/bin/sh
+
+. /lib/functions/uci-defaults.sh
+
+board_config_update
+
+board=$(board_name)
+
+board_config_flush
+
+exit 0
diff --git a/target/linux/ramips/rt6855a/config-5.4 b/target/linux/ramips/rt6855a/config-5.4
new file mode 100644
index 0000000000..fb810bc412
--- /dev/null
+++ b/target/linux/ramips/rt6855a/config-5.4
@@ -0,0 +1,2531 @@
+#
+# Automatically generated file; DO NOT EDIT.
+# Linux/mips 5.4.82 Kernel Configuration
+#
+
+#
+# Compiler: mipsel-openwrt-linux-musl-gcc (OpenWrt GCC 10.2.0 r15181+9-a3e5b24d43) 10.2.0
+#
+CONFIG_CC_IS_GCC=y
+CONFIG_GCC_VERSION=100200
+CONFIG_CLANG_VERSION=0
+CONFIG_CC_CAN_LINK=y
+CONFIG_CC_HAS_ASM_GOTO=y
+CONFIG_CC_HAS_ASM_INLINE=y
+CONFIG_IRQ_WORK=y
+CONFIG_BUILDTIME_EXTABLE_SORT=y
+
+#
+# General setup
+#
+CONFIG_BROKEN_ON_SMP=y
+CONFIG_INIT_ENV_ARG_LIMIT=32
+# CONFIG_COMPILE_TEST is not set
+CONFIG_LOCALVERSION=""
+CONFIG_LOCALVERSION_AUTO=y
+CONFIG_BUILD_SALT=""
+CONFIG_HAVE_KERNEL_GZIP=y
+CONFIG_HAVE_KERNEL_BZIP2=y
+CONFIG_HAVE_KERNEL_LZMA=y
+CONFIG_HAVE_KERNEL_XZ=y
+CONFIG_HAVE_KERNEL_LZO=y
+CONFIG_HAVE_KERNEL_LZ4=y
+# CONFIG_KERNEL_GZIP is not set
+# CONFIG_KERNEL_BZIP2 is not set
+# CONFIG_KERNEL_LZMA is not set
+CONFIG_KERNEL_XZ=y
+# CONFIG_KERNEL_LZO is not set
+# CONFIG_KERNEL_LZ4 is not set
+CONFIG_DEFAULT_HOSTNAME="(none)"
+CONFIG_SYSVIPC=y
+CONFIG_SYSVIPC_SYSCTL=y
+CONFIG_POSIX_MQUEUE=y
+CONFIG_POSIX_MQUEUE_SYSCTL=y
+CONFIG_CROSS_MEMORY_ATTACH=y
+# CONFIG_USELIB is not set
+# CONFIG_AUDIT is not set
+
+#
+# IRQ subsystem
+#
+CONFIG_GENERIC_IRQ_PROBE=y
+CONFIG_GENERIC_IRQ_SHOW=y
+CONFIG_GENERIC_IRQ_EFFECTIVE_AFF_MASK=y
+CONFIG_GENERIC_IRQ_CHIP=y
+CONFIG_IRQ_DOMAIN=y
+CONFIG_HANDLE_DOMAIN_IRQ=y
+CONFIG_IRQ_FORCED_THREADING=y
+# CONFIG_GENERIC_IRQ_DEBUGFS is not set
+# end of IRQ subsystem
+
+CONFIG_ARCH_CLOCKSOURCE_DATA=y
+CONFIG_GENERIC_TIME_VSYSCALL=y
+CONFIG_GENERIC_CLOCKEVENTS=y
+CONFIG_GENERIC_CMOS_UPDATE=y
+
+#
+# Timers subsystem
+#
+CONFIG_HZ_PERIODIC=y
+# CONFIG_NO_HZ_IDLE is not set
+# CONFIG_NO_HZ is not set
+# CONFIG_HIGH_RES_TIMERS is not set
+# end of Timers subsystem
+
+CONFIG_PREEMPT_NONE=y
+# CONFIG_PREEMPT_VOLUNTARY is not set
+# CONFIG_PREEMPT is not set
+
+#
+# CPU/Task time and stats accounting
+#
+CONFIG_TICK_CPU_ACCOUNTING=y
+# CONFIG_VIRT_CPU_ACCOUNTING_GEN is not set
+# CONFIG_IRQ_TIME_ACCOUNTING is not set
+# CONFIG_BSD_PROCESS_ACCT is not set
+# CONFIG_TASKSTATS is not set
+# CONFIG_PSI is not set
+# end of CPU/Task time and stats accounting
+
+#
+# RCU Subsystem
+#
+CONFIG_TINY_RCU=y
+# CONFIG_RCU_EXPERT is not set
+CONFIG_SRCU=y
+CONFIG_TINY_SRCU=y
+# end of RCU Subsystem
+
+# CONFIG_IKCONFIG is not set
+# CONFIG_IKHEADERS is not set
+CONFIG_LOG_BUF_SHIFT=14
+CONFIG_PRINTK_SAFE_LOG_BUF_SHIFT=13
+CONFIG_GENERIC_SCHED_CLOCK=y
+
+#
+# Scheduler features
+#
+# end of Scheduler features
+
+CONFIG_CGROUPS=y
+CONFIG_PAGE_COUNTER=y
+CONFIG_MEMCG=y
+CONFIG_MEMCG_KMEM=y
+CONFIG_CGROUP_SCHED=y
+CONFIG_FAIR_GROUP_SCHED=y
+CONFIG_CFS_BANDWIDTH=y
+CONFIG_RT_GROUP_SCHED=y
+CONFIG_CGROUP_PIDS=y
+CONFIG_CGROUP_RDMA=y
+# CONFIG_CGROUP_FREEZER is not set
+# CONFIG_CGROUP_DEVICE is not set
+CONFIG_CGROUP_CPUACCT=y
+# CONFIG_CGROUP_DEBUG is not set
+CONFIG_NAMESPACES=y
+CONFIG_UTS_NS=y
+CONFIG_IPC_NS=y
+CONFIG_USER_NS=y
+CONFIG_PID_NS=y
+CONFIG_NET_NS=y
+# CONFIG_CHECKPOINT_RESTORE is not set
+# CONFIG_SCHED_AUTOGROUP is not set
+# CONFIG_SYSFS_DEPRECATED is not set
+# CONFIG_RELAY is not set
+CONFIG_BLK_DEV_INITRD=y
+CONFIG_INITRAMFS_SOURCE=""
+# CONFIG_RD_GZIP is not set
+# CONFIG_RD_BZIP2 is not set
+CONFIG_RD_LZMA=y
+# CONFIG_RD_XZ is not set
+# CONFIG_RD_LZO is not set
+# CONFIG_RD_LZ4 is not set
+CONFIG_CC_OPTIMIZE_FOR_PERFORMANCE=y
+# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set
+CONFIG_HAVE_LD_DEAD_CODE_DATA_ELIMINATION=y
+# CONFIG_LD_DEAD_CODE_DATA_ELIMINATION is not set
+CONFIG_SYSCTL=y
+CONFIG_SYSCTL_EXCEPTION_TRACE=y
+CONFIG_KALLSYMS_UNCOMPRESSED=y
+CONFIG_BPF=y
+CONFIG_EXPERT=y
+CONFIG_MULTIUSER=y
+CONFIG_SGETMASK_SYSCALL=y
+CONFIG_SYSFS_SYSCALL=y
+# CONFIG_SYSCTL_SYSCALL is not set
+CONFIG_FHANDLE=y
+CONFIG_POSIX_TIMERS=y
+CONFIG_PRINTK=y
+CONFIG_PRINTK_NMI=y
+CONFIG_BUG=y
+CONFIG_ELF_CORE=y
+CONFIG_BASE_FULL=y
+CONFIG_FUTEX=y
+CONFIG_FUTEX_PI=y
+CONFIG_EPOLL=y
+CONFIG_SIGNALFD=y
+CONFIG_TIMERFD=y
+CONFIG_EVENTFD=y
+CONFIG_SHMEM=y
+CONFIG_AIO=y
+CONFIG_IO_URING=y
+CONFIG_ADVISE_SYSCALLS=y
+CONFIG_MEMBARRIER=y
+CONFIG_KALLSYMS=y
+# CONFIG_KALLSYMS_ALL is not set
+CONFIG_KALLSYMS_BASE_RELATIVE=y
+# CONFIG_BPF_SYSCALL is not set
+# CONFIG_USERFAULTFD is not set
+CONFIG_RSEQ=y
+# CONFIG_DEBUG_RSEQ is not set
+CONFIG_EMBEDDED=y
+# CONFIG_MANGLE_BOOTARGS is not set
+CONFIG_HAVE_PERF_EVENTS=y
+CONFIG_PERF_USE_VMALLOC=y
+# CONFIG_PC104 is not set
+
+#
+# Kernel Performance Events And Counters
+#
+# CONFIG_PERF_EVENTS is not set
+# end of Kernel Performance Events And Counters
+
+# CONFIG_VM_EVENT_COUNTERS is not set
+CONFIG_COMPAT_BRK=y
+CONFIG_SLAB=y
+# CONFIG_SLUB is not set
+# CONFIG_SLOB is not set
+CONFIG_SLAB_MERGE_DEFAULT=y
+# CONFIG_SLAB_FREELIST_RANDOM is not set
+# CONFIG_SHUFFLE_PAGE_ALLOCATOR is not set
+CONFIG_SYSTEM_DATA_VERIFICATION=y
+# CONFIG_PROFILING is not set
+# end of General setup
+
+CONFIG_MIPS=y
+
+#
+# Machine selection
+#
+# CONFIG_MIPS_GENERIC is not set
+# CONFIG_MIPS_ALCHEMY is not set
+# CONFIG_AR7 is not set
+# CONFIG_ATH25 is not set
+# CONFIG_ATH79 is not set
+# CONFIG_BMIPS_GENERIC is not set
+# CONFIG_BCM47XX is not set
+# CONFIG_BCM63XX is not set
+# CONFIG_MIPS_COBALT is not set
+# CONFIG_MACH_DECSTATION is not set
+# CONFIG_MACH_JAZZ is not set
+# CONFIG_MACH_INGENIC is not set
+# CONFIG_LANTIQ is not set
+# CONFIG_LASAT is not set
+# CONFIG_MACH_LOONGSON32 is not set
+# CONFIG_MACH_LOONGSON64 is not set
+# CONFIG_MACH_PISTACHIO is not set
+# CONFIG_MIPS_MALTA is not set
+# CONFIG_MACH_PIC32 is not set
+# CONFIG_NEC_MARKEINS is not set
+# CONFIG_MACH_VR41XX is not set
+# CONFIG_NXP_STB220 is not set
+# CONFIG_NXP_STB225 is not set
+# CONFIG_PMC_MSP is not set
+CONFIG_RALINK=y
+# CONFIG_SGI_IP22 is not set
+# CONFIG_SGI_IP27 is not set
+# CONFIG_SGI_IP28 is not set
+# CONFIG_SGI_IP32 is not set
+# CONFIG_SIBYTE_CRHINE is not set
+# CONFIG_SIBYTE_CARMEL is not set
+# CONFIG_SIBYTE_CRHONE is not set
+# CONFIG_SIBYTE_RHONE is not set
+# CONFIG_SIBYTE_SWARM is not set
+# CONFIG_SIBYTE_LITTLESUR is not set
+# CONFIG_SIBYTE_SENTOSA is not set
+# CONFIG_SIBYTE_BIGSUR is not set
+# CONFIG_SNI_RM is not set
+# CONFIG_MACH_TX39XX is not set
+# CONFIG_MACH_TX49XX is not set
+# CONFIG_MIKROTIK_RB532 is not set
+# CONFIG_CAVIUM_OCTEON_SOC is not set
+# CONFIG_NLM_XLR_BOARD is not set
+# CONFIG_NLM_XLP_BOARD is not set
+# CONFIG_MIPS_PARAVIRT is not set
+# CONFIG_SOC_RT288X is not set
+# CONFIG_SOC_RT305X is not set
+# CONFIG_SOC_RT3883 is not set
+CONFIG_SOC_RT6855=y
+# CONFIG_SOC_MT7620 is not set
+# CONFIG_SOC_MT7621 is not set
+# CONFIG_DTB_RT_NONE is not set
+CONFIG_DTB_WAP300N=y
+# end of Machine selection
+
+CONFIG_GENERIC_HWEIGHT=y
+CONFIG_GENERIC_CALIBRATE_DELAY=y
+CONFIG_SCHED_OMIT_FRAME_POINTER=y
+CONFIG_CEVT_R4K=y
+CONFIG_CSRC_R4K=y
+CONFIG_MIPS_CLOCK_VSYSCALL=y
+CONFIG_ARCH_SUPPORTS_UPROBES=y
+CONFIG_DMA_NONCOHERENT=y
+CONFIG_SYS_HAS_EARLY_PRINTK=y
+# CONFIG_IMAGE_CMDLINE_HACK is not set
+CONFIG_MIPS_CBPF_JIT=y
+CONFIG_CPU_LITTLE_ENDIAN=y
+CONFIG_SYS_SUPPORTS_LITTLE_ENDIAN=y
+CONFIG_MIPS_SPRAM=y
+CONFIG_MIPS_L1_CACHE_SHIFT=5
+
+#
+# CPU selection
+#
+# CONFIG_CPU_MIPS32_R1 is not set
+CONFIG_CPU_MIPS32_R2=y
+CONFIG_SYS_SUPPORTS_ZBOOT=y
+CONFIG_SYS_HAS_CPU_MIPS32_R1=y
+CONFIG_SYS_HAS_CPU_MIPS32_R2=y
+# end of CPU selection
+
+CONFIG_CPU_MIPS32=y
+CONFIG_CPU_MIPSR2=y
+CONFIG_TARGET_ISA_REV=2
+CONFIG_SYS_SUPPORTS_32BIT_KERNEL=y
+CONFIG_CPU_SUPPORTS_32BIT_KERNEL=y
+CONFIG_HARDWARE_WATCHPOINTS=y
+
+#
+# Kernel type
+#
+CONFIG_32BIT=y
+# CONFIG_KVM_GUEST is not set
+CONFIG_PAGE_SIZE_4KB=y
+# CONFIG_PAGE_SIZE_16KB is not set
+# CONFIG_PAGE_SIZE_64KB is not set
+CONFIG_FORCE_MAX_ZONEORDER=11
+CONFIG_CPU_HAS_PREFETCH=y
+CONFIG_CPU_GENERIC_DUMP_TLB=y
+CONFIG_MIPS_FP_SUPPORT=y
+CONFIG_CPU_R4K_FPU=y
+CONFIG_CPU_R4K_CACHE_TLB=y
+CONFIG_CPU_NEEDS_NO_SMARTMIPS_OR_MICROMIPS=y
+CONFIG_CPU_HAS_RIXI=y
+CONFIG_CPU_HAS_LOAD_STORE_LR=y
+CONFIG_CPU_HAS_SYNC=y
+CONFIG_MIPS_ASID_SHIFT=0
+CONFIG_MIPS_ASID_BITS=8
+CONFIG_CPU_SUPPORTS_HIGHMEM=y
+CONFIG_SYS_SUPPORTS_MIPS16=y
+CONFIG_CPU_SUPPORTS_MSA=y
+CONFIG_ARCH_FLATMEM_ENABLE=y
+# CONFIG_HZ_24 is not set
+# CONFIG_HZ_48 is not set
+CONFIG_HZ_100=y
+# CONFIG_HZ_128 is not set
+# CONFIG_HZ_250 is not set
+# CONFIG_HZ_256 is not set
+# CONFIG_HZ_1000 is not set
+# CONFIG_HZ_1024 is not set
+CONFIG_SYS_SUPPORTS_ARBIT_HZ=y
+CONFIG_HZ=100
+# CONFIG_KEXEC is not set
+# CONFIG_CRASH_DUMP is not set
+CONFIG_SECCOMP=y
+# CONFIG_MIPS_O32_FP64_SUPPORT is not set
+CONFIG_USE_OF=y
+CONFIG_BUILTIN_DTB=y
+# CONFIG_MIPS_NO_APPENDED_DTB is not set
+CONFIG_MIPS_ELF_APPENDED_DTB=y
+# CONFIG_MIPS_RAW_APPENDED_DTB is not set
+# CONFIG_MIPS_CMDLINE_FROM_DTB is not set
+# CONFIG_MIPS_CMDLINE_DTB_EXTEND is not set
+CONFIG_MIPS_CMDLINE_FROM_BOOTLOADER=y
+# CONFIG_MIPS_CMDLINE_BUILTIN_EXTEND is not set
+CONFIG_BOOT_RAW=y
+# end of Kernel type
+
+CONFIG_LOCKDEP_SUPPORT=y
+CONFIG_STACKTRACE_SUPPORT=y
+CONFIG_PGTABLE_LEVELS=2
+
+#
+# Bus options (PCI, PCMCIA, EISA, ISA, TC)
+#
+CONFIG_PCI_DRIVERS_LEGACY=y
+CONFIG_MMU=y
+CONFIG_ARCH_MMAP_RND_BITS_MIN=8
+CONFIG_ARCH_MMAP_RND_BITS_MAX=15
+CONFIG_ARCH_MMAP_RND_COMPAT_BITS_MIN=8
+CONFIG_ARCH_MMAP_RND_COMPAT_BITS_MAX=15
+# end of Bus options (PCI, PCMCIA, EISA, ISA, TC)
+
+CONFIG_TRAD_SIGNALS=y
+
+#
+# Power management options
+#
+CONFIG_ARCH_HIBERNATION_POSSIBLE=y
+CONFIG_ARCH_SUSPEND_POSSIBLE=y
+# CONFIG_SUSPEND is not set
+# CONFIG_PM is not set
+# end of Power management options
+
+#
+# CPU Power Management
+#
+
+#
+# CPU Idle
+#
+# CONFIG_CPU_IDLE is not set
+# end of CPU Idle
+# end of CPU Power Management
+
+#
+# Firmware Drivers
+#
+# CONFIG_FIRMWARE_MEMMAP is not set
+# CONFIG_GOOGLE_FIRMWARE is not set
+
+#
+# Tegra firmware driver
+#
+# end of Tegra firmware driver
+# end of Firmware Drivers
+
+CONFIG_HAVE_KVM=y
+# CONFIG_VIRTUALIZATION is not set
+
+#
+# General architecture-dependent options
+#
+CONFIG_HAVE_OPROFILE=y
+# CONFIG_KPROBES is not set
+# CONFIG_JUMP_LABEL is not set
+CONFIG_ARCH_USE_BUILTIN_BSWAP=y
+CONFIG_HAVE_IOREMAP_PROT=y
+CONFIG_HAVE_KPROBES=y
+CONFIG_HAVE_KRETPROBES=y
+CONFIG_HAVE_NMI=y
+CONFIG_HAVE_ARCH_TRACEHOOK=y
+CONFIG_HAVE_DMA_CONTIGUOUS=y
+CONFIG_GENERIC_SMP_IDLE_THREAD=y
+CONFIG_ARCH_HAS_UNCACHED_SEGMENT=y
+CONFIG_ARCH_32BIT_OFF_T=y
+CONFIG_HAVE_ASM_MODVERSIONS=y
+CONFIG_HAVE_REGS_AND_STACK_ACCESS_API=y
+CONFIG_HAVE_RSEQ=y
+CONFIG_HAVE_CLK=y
+CONFIG_HAVE_ARCH_JUMP_LABEL=y
+CONFIG_ARCH_WANT_IPC_PARSE_VERSION=y
+CONFIG_HAVE_ARCH_SECCOMP_FILTER=y
+CONFIG_SECCOMP_FILTER=y
+CONFIG_HAVE_STACKPROTECTOR=y
+CONFIG_CC_HAS_STACKPROTECTOR_NONE=y
+CONFIG_STACKPROTECTOR=y
+# CONFIG_STACKPROTECTOR_STRONG is not set
+CONFIG_HAVE_CONTEXT_TRACKING=y
+CONFIG_HAVE_VIRT_CPU_ACCOUNTING_GEN=y
+CONFIG_HAVE_IRQ_TIME_ACCOUNTING=y
+CONFIG_HAVE_MOD_ARCH_SPECIFIC=y
+CONFIG_MODULES_USE_ELF_REL=y
+CONFIG_HAVE_IRQ_EXIT_ON_IRQ_STACK=y
+CONFIG_ARCH_HAS_ELF_RANDOMIZE=y
+CONFIG_HAVE_ARCH_MMAP_RND_BITS=y
+CONFIG_HAVE_EXIT_THREAD=y
+CONFIG_ARCH_MMAP_RND_BITS=8
+CONFIG_ARCH_WANT_DEFAULT_TOPDOWN_MMAP_LAYOUT=y
+CONFIG_HAVE_COPY_THREAD_TLS=y
+CONFIG_CLONE_BACKWARDS=y
+CONFIG_64BIT_TIME=y
+CONFIG_COMPAT_32BIT_TIME=y
+# CONFIG_REFCOUNT_FULL is not set
+CONFIG_HAVE_ARCH_COMPILER_H=y
+# CONFIG_LOCK_EVENT_COUNTS is not set
+
+#
+# GCOV-based kernel profiling
+#
+# CONFIG_GCOV_KERNEL is not set
+# end of GCOV-based kernel profiling
+
+CONFIG_PLUGIN_HOSTCC=""
+# end of General architecture-dependent options
+
+CONFIG_RT_MUTEXES=y
+CONFIG_BASE_SMALL=0
+CONFIG_MODULES=y
+# CONFIG_MODULE_FORCE_LOAD is not set
+CONFIG_MODULE_UNLOAD=y
+# CONFIG_MODULE_FORCE_UNLOAD is not set
+# CONFIG_MODVERSIONS is not set
+# CONFIG_MODULE_SRCVERSION_ALL is not set
+# CONFIG_MODULE_SIG is not set
+# CONFIG_MODULE_COMPRESS is not set
+# CONFIG_MODULE_ALLOW_MISSING_NAMESPACE_IMPORTS is not set
+# CONFIG_UNUSED_SYMBOLS is not set
+# CONFIG_TRIM_UNUSED_KSYMS is not set
+CONFIG_MODULE_STRIPPED=y
+# CONFIG_BLOCK is not set
+CONFIG_ASN1=y
+CONFIG_INLINE_SPIN_UNLOCK_IRQ=y
+CONFIG_INLINE_READ_UNLOCK=y
+CONFIG_INLINE_READ_UNLOCK_IRQ=y
+CONFIG_INLINE_WRITE_UNLOCK=y
+CONFIG_INLINE_WRITE_UNLOCK_IRQ=y
+CONFIG_ARCH_USE_QUEUED_SPINLOCKS=y
+CONFIG_ARCH_USE_QUEUED_RWLOCKS=y
+
+#
+# Executable file formats
+#
+CONFIG_BINFMT_ELF=y
+CONFIG_ARCH_BINFMT_ELF_STATE=y
+CONFIG_ELFCORE=y
+# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set
+CONFIG_BINFMT_SCRIPT=y
+# CONFIG_BINFMT_MISC is not set
+CONFIG_COREDUMP=y
+# end of Executable file formats
+
+#
+# Memory Management options
+#
+CONFIG_FLATMEM=y
+CONFIG_FLAT_NODE_MEM_MAP=y
+CONFIG_HAVE_MEMBLOCK_NODE_MAP=y
+CONFIG_HAVE_FAST_GUP=y
+CONFIG_SPLIT_PTLOCK_CPUS=4
+CONFIG_COMPACTION=y
+CONFIG_MIGRATION=y
+CONFIG_VIRT_TO_BUS=y
+# CONFIG_KSM is not set
+CONFIG_DEFAULT_MMAP_MIN_ADDR=4096
+CONFIG_NEED_PER_CPU_KM=y
+# CONFIG_CLEANCACHE is not set
+# CONFIG_CMA is not set
+# CONFIG_ZPOOL is not set
+# CONFIG_ZBUD is not set
+# CONFIG_ZSMALLOC is not set
+# CONFIG_IDLE_PAGE_TRACKING is not set
+# CONFIG_PERCPU_STATS is not set
+# CONFIG_GUP_BENCHMARK is not set
+# end of Memory Management options
+
+CONFIG_NET=y
+CONFIG_NET_INGRESS=y
+
+#
+# Networking options
+#
+CONFIG_PACKET=y
+# CONFIG_PACKET_DIAG is not set
+CONFIG_UNIX=y
+CONFIG_UNIX_SCM=y
+# CONFIG_UNIX_DIAG is not set
+# CONFIG_TLS is not set
+# CONFIG_XFRM_USER is not set
+# CONFIG_NET_KEY is not set
+CONFIG_INET=y
+# CONFIG_IP_MULTICAST is not set
+# CONFIG_IP_ADVANCED_ROUTER is not set
+# CONFIG_IP_PNP is not set
+# CONFIG_NET_IPIP is not set
+# CONFIG_NET_IPGRE_DEMUX is not set
+CONFIG_NET_IP_TUNNEL=y
+CONFIG_IP_MROUTE_COMMON=y
+# CONFIG_SYN_COOKIES is not set
+# CONFIG_NET_IPVTI is not set
+# CONFIG_NET_FOU is not set
+# CONFIG_NET_FOU_IP_TUNNELS is not set
+# CONFIG_INET_AH is not set
+# CONFIG_INET_ESP is not set
+# CONFIG_INET_IPCOMP is not set
+CONFIG_INET_TUNNEL=y
+CONFIG_INET_DIAG=y
+CONFIG_INET_TCP_DIAG=y
+# CONFIG_INET_UDP_DIAG is not set
+# CONFIG_INET_RAW_DIAG is not set
+# CONFIG_INET_DIAG_DESTROY is not set
+# CONFIG_TCP_CONG_ADVANCED is not set
+CONFIG_TCP_CONG_CUBIC=y
+CONFIG_DEFAULT_TCP_CONG="cubic"
+# CONFIG_TCP_MD5SIG is not set
+CONFIG_IPV6=y
+# CONFIG_IPV6_ROUTER_PREF is not set
+# CONFIG_IPV6_OPTIMISTIC_DAD is not set
+# CONFIG_INET6_AH is not set
+# CONFIG_INET6_ESP is not set
+# CONFIG_INET6_IPCOMP is not set
+# CONFIG_IPV6_MIP6 is not set
+# CONFIG_IPV6_ILA is not set
+# CONFIG_IPV6_VTI is not set
+CONFIG_IPV6_SIT=y
+# CONFIG_IPV6_SIT_6RD is not set
+CONFIG_IPV6_NDISC_NODETYPE=y
+# CONFIG_IPV6_TUNNEL is not set
+CONFIG_IPV6_MULTIPLE_TABLES=y
+CONFIG_IPV6_SUBTREES=y
+CONFIG_IPV6_MROUTE=y
+# CONFIG_IPV6_MROUTE_MULTIPLE_TABLES is not set
+# CONFIG_IPV6_PIMSM_V2 is not set
+# CONFIG_IPV6_SEG6_LWTUNNEL is not set
+# CONFIG_IPV6_SEG6_HMAC is not set
+CONFIG_SOCK_DIAG=y
+# CONFIG_NETWORK_SECMARK is not set
+# CONFIG_NETWORK_PHY_TIMESTAMPING is not set
+CONFIG_NETFILTER=y
+CONFIG_NETFILTER_ADVANCED=y
+
+#
+# Core Netfilter Configuration
+#
+CONFIG_NETFILTER_INGRESS=y
+# CONFIG_NETFILTER_NETLINK is not set
+# CONFIG_NETFILTER_NETLINK_ACCT is not set
+# CONFIG_NETFILTER_NETLINK_QUEUE is not set
+# CONFIG_NETFILTER_NETLINK_LOG is not set
+# CONFIG_NETFILTER_NETLINK_OSF is not set
+CONFIG_NF_CONNTRACK=m
+CONFIG_NF_LOG_COMMON=m
+# CONFIG_NF_LOG_NETDEV is not set
+CONFIG_NF_CONNTRACK_MARK=y
+CONFIG_NF_CONNTRACK_ZONES=y
+CONFIG_NF_CONNTRACK_PROCFS=y
+# CONFIG_NF_CONNTRACK_EVENTS is not set
+CONFIG_NF_CONNTRACK_RTCACHE=m
+# CONFIG_NF_CONNTRACK_TIMEOUT is not set
+# CONFIG_NF_CONNTRACK_TIMESTAMP is not set
+# CONFIG_NF_CONNTRACK_LABELS is not set
+# CONFIG_NF_CT_PROTO_DCCP is not set
+# CONFIG_NF_CT_PROTO_SCTP is not set
+# CONFIG_NF_CT_PROTO_UDPLITE is not set
+# CONFIG_NF_CONNTRACK_AMANDA is not set
+# CONFIG_NF_CONNTRACK_FTP is not set
+# CONFIG_NF_CONNTRACK_H323 is not set
+# CONFIG_NF_CONNTRACK_IRC is not set
+# CONFIG_NF_CONNTRACK_NETBIOS_NS is not set
+# CONFIG_NF_CONNTRACK_SNMP is not set
+# CONFIG_NF_CONNTRACK_PPTP is not set
+# CONFIG_NF_CONNTRACK_SANE is not set
+# CONFIG_NF_CONNTRACK_SIP is not set
+# CONFIG_NF_CONNTRACK_TFTP is not set
+# CONFIG_NF_CT_NETLINK is not set
+CONFIG_NF_NAT=m
+CONFIG_NF_NAT_REDIRECT=y
+CONFIG_NF_NAT_MASQUERADE=y
+# CONFIG_NF_TABLES is not set
+CONFIG_NF_FLOW_TABLE=m
+CONFIG_NF_FLOW_TABLE_HW=m
+CONFIG_NETFILTER_XTABLES=m
+
+#
+# Xtables combined modules
+#
+CONFIG_NETFILTER_XT_MARK=m
+# CONFIG_NETFILTER_XT_CONNMARK is not set
+
+#
+# Xtables targets
+#
+# CONFIG_NETFILTER_XT_TARGET_CHECKSUM is not set
+# CONFIG_NETFILTER_XT_TARGET_CLASSIFY is not set
+# CONFIG_NETFILTER_XT_TARGET_CONNMARK is not set
+# CONFIG_NETFILTER_XT_TARGET_DSCP is not set
+# CONFIG_NETFILTER_XT_TARGET_HL is not set
+# CONFIG_NETFILTER_XT_TARGET_HMARK is not set
+# CONFIG_NETFILTER_XT_TARGET_IDLETIMER is not set
+CONFIG_NETFILTER_XT_TARGET_LOG=m
+# CONFIG_NETFILTER_XT_TARGET_MARK is not set
+CONFIG_NETFILTER_XT_NAT=m
+# CONFIG_NETFILTER_XT_TARGET_NETMAP is not set
+# CONFIG_NETFILTER_XT_TARGET_NFLOG is not set
+# CONFIG_NETFILTER_XT_TARGET_NFQUEUE is not set
+CONFIG_NETFILTER_XT_TARGET_FLOWOFFLOAD=m
+# CONFIG_NETFILTER_XT_TARGET_RATEEST is not set
+CONFIG_NETFILTER_XT_TARGET_REDIRECT=m
+CONFIG_NETFILTER_XT_TARGET_MASQUERADE=m
+# CONFIG_NETFILTER_XT_TARGET_TEE is not set
+# CONFIG_NETFILTER_XT_TARGET_TPROXY is not set
+CONFIG_NETFILTER_XT_TARGET_TCPMSS=m
+# CONFIG_NETFILTER_XT_TARGET_TCPOPTSTRIP is not set
+
+#
+# Xtables matches
+#
+# CONFIG_NETFILTER_XT_MATCH_ADDRTYPE is not set
+# CONFIG_NETFILTER_XT_MATCH_BPF is not set
+# CONFIG_NETFILTER_XT_MATCH_CGROUP is not set
+# CONFIG_NETFILTER_XT_MATCH_CLUSTER is not set
+CONFIG_NETFILTER_XT_MATCH_COMMENT=m
+# CONFIG_NETFILTER_XT_MATCH_CONNBYTES is not set
+# CONFIG_NETFILTER_XT_MATCH_CONNLABEL is not set
+# CONFIG_NETFILTER_XT_MATCH_CONNLIMIT is not set
+# CONFIG_NETFILTER_XT_MATCH_CONNMARK is not set
+CONFIG_NETFILTER_XT_MATCH_CONNTRACK=m
+# CONFIG_NETFILTER_XT_MATCH_CPU is not set
+# CONFIG_NETFILTER_XT_MATCH_DCCP is not set
+# CONFIG_NETFILTER_XT_MATCH_DEVGROUP is not set
+# CONFIG_NETFILTER_XT_MATCH_DSCP is not set
+# CONFIG_NETFILTER_XT_MATCH_ECN is not set
+# CONFIG_NETFILTER_XT_MATCH_ESP is not set
+# CONFIG_NETFILTER_XT_MATCH_HASHLIMIT is not set
+# CONFIG_NETFILTER_XT_MATCH_HELPER is not set
+# CONFIG_NETFILTER_XT_MATCH_HL is not set
+# CONFIG_NETFILTER_XT_MATCH_IPCOMP is not set
+# CONFIG_NETFILTER_XT_MATCH_IPRANGE is not set
+# CONFIG_NETFILTER_XT_MATCH_L2TP is not set
+# CONFIG_NETFILTER_XT_MATCH_LENGTH is not set
+CONFIG_NETFILTER_XT_MATCH_LIMIT=m
+CONFIG_NETFILTER_XT_MATCH_MAC=m
+# CONFIG_NETFILTER_XT_MATCH_MARK is not set
+CONFIG_NETFILTER_XT_MATCH_MULTIPORT=m
+# CONFIG_NETFILTER_XT_MATCH_NFACCT is not set
+# CONFIG_NETFILTER_XT_MATCH_OSF is not set
+# CONFIG_NETFILTER_XT_MATCH_OWNER is not set
+# CONFIG_NETFILTER_XT_MATCH_PKTTYPE is not set
+# CONFIG_NETFILTER_XT_MATCH_QUOTA is not set
+# CONFIG_NETFILTER_XT_MATCH_RATEEST is not set
+# CONFIG_NETFILTER_XT_MATCH_REALM is not set
+# CONFIG_NETFILTER_XT_MATCH_RECENT is not set
+# CONFIG_NETFILTER_XT_MATCH_SCTP is not set
+# CONFIG_NETFILTER_XT_MATCH_SOCKET is not set
+CONFIG_NETFILTER_XT_MATCH_STATE=m
+# CONFIG_NETFILTER_XT_MATCH_STATISTIC is not set
+# CONFIG_NETFILTER_XT_MATCH_STRING is not set
+# CONFIG_NETFILTER_XT_MATCH_TCPMSS is not set
+CONFIG_NETFILTER_XT_MATCH_TIME=m
+# CONFIG_NETFILTER_XT_MATCH_U32 is not set
+# end of Core Netfilter Configuration
+
+# CONFIG_IP_SET is not set
+# CONFIG_IP_VS is not set
+
+#
+# IP: Netfilter Configuration
+#
+CONFIG_NF_DEFRAG_IPV4=m
+# CONFIG_NF_SOCKET_IPV4 is not set
+# CONFIG_NF_TPROXY_IPV4 is not set
+# CONFIG_NF_DUP_IPV4 is not set
+# CONFIG_NF_LOG_ARP is not set
+CONFIG_NF_LOG_IPV4=m
+CONFIG_NF_REJECT_IPV4=m
+CONFIG_IP_NF_IPTABLES=m
+# CONFIG_IP_NF_MATCH_AH is not set
+# CONFIG_IP_NF_MATCH_ECN is not set
+# CONFIG_IP_NF_MATCH_RPFILTER is not set
+# CONFIG_IP_NF_MATCH_TTL is not set
+CONFIG_IP_NF_FILTER=m
+CONFIG_IP_NF_TARGET_REJECT=m
+# CONFIG_IP_NF_TARGET_SYNPROXY is not set
+CONFIG_IP_NF_NAT=m
+# CONFIG_IP_NF_TARGET_MASQUERADE is not set
+# CONFIG_IP_NF_TARGET_NETMAP is not set
+# CONFIG_IP_NF_TARGET_REDIRECT is not set
+CONFIG_IP_NF_MANGLE=m
+# CONFIG_IP_NF_TARGET_CLUSTERIP is not set
+# CONFIG_IP_NF_TARGET_ECN is not set
+# CONFIG_IP_NF_TARGET_TTL is not set
+# CONFIG_IP_NF_RAW is not set
+# CONFIG_IP_NF_ARPTABLES is not set
+# end of IP: Netfilter Configuration
+
+#
+# IPv6: Netfilter Configuration
+#
+# CONFIG_NF_SOCKET_IPV6 is not set
+# CONFIG_NF_TPROXY_IPV6 is not set
+# CONFIG_NF_DUP_IPV6 is not set
+CONFIG_NF_REJECT_IPV6=m
+CONFIG_NF_LOG_IPV6=m
+CONFIG_IP6_NF_IPTABLES=m
+# CONFIG_IP6_NF_MATCH_AH is not set
+# CONFIG_IP6_NF_MATCH_EUI64 is not set
+# CONFIG_IP6_NF_MATCH_FRAG is not set
+# CONFIG_IP6_NF_MATCH_OPTS is not set
+# CONFIG_IP6_NF_MATCH_HL is not set
+# CONFIG_IP6_NF_MATCH_IPV6HEADER is not set
+# CONFIG_IP6_NF_MATCH_MH is not set
+# CONFIG_IP6_NF_MATCH_RPFILTER is not set
+# CONFIG_IP6_NF_MATCH_RT is not set
+# CONFIG_IP6_NF_MATCH_SRH is not set
+# CONFIG_IP6_NF_TARGET_HL is not set
+CONFIG_IP6_NF_FILTER=m
+CONFIG_IP6_NF_TARGET_REJECT=m
+# CONFIG_IP6_NF_TARGET_SYNPROXY is not set
+CONFIG_IP6_NF_MANGLE=m
+# CONFIG_IP6_NF_RAW is not set
+# CONFIG_IP6_NF_NAT is not set
+# end of IPv6: Netfilter Configuration
+
+CONFIG_NF_DEFRAG_IPV6=m
+# CONFIG_NF_CONNTRACK_BRIDGE is not set
+# CONFIG_BPFILTER is not set
+# CONFIG_IP_DCCP is not set
+# CONFIG_IP_SCTP is not set
+# CONFIG_RDS is not set
+# CONFIG_TIPC is not set
+# CONFIG_ATM is not set
+# CONFIG_L2TP is not set
+CONFIG_BRIDGE=y
+CONFIG_HAVE_NET_DSA=y
+# CONFIG_NET_DSA is not set
+# CONFIG_VLAN_8021Q is not set
+# CONFIG_DECNET is not set
+# CONFIG_LLC2 is not set
+# CONFIG_ATALK is not set
+# CONFIG_X25 is not set
+# CONFIG_LAPB is not set
+# CONFIG_PHONET is not set
+# CONFIG_6LOWPAN is not set
+# CONFIG_IEEE802154 is not set
+CONFIG_NET_SCHED=y
+
+#
+# Queueing/Scheduling
+#
+# CONFIG_NET_SCH_CBQ is not set
+# CONFIG_NET_SCH_HTB is not set
+# CONFIG_NET_SCH_HFSC is not set
+# CONFIG_NET_SCH_PRIO is not set
+# CONFIG_NET_SCH_MULTIQ is not set
+# CONFIG_NET_SCH_RED is not set
+# CONFIG_NET_SCH_SFB is not set
+# CONFIG_NET_SCH_SFQ is not set
+# CONFIG_NET_SCH_TEQL is not set
+# CONFIG_NET_SCH_TBF is not set
+# CONFIG_NET_SCH_CBS is not set
+# CONFIG_NET_SCH_ETF is not set
+# CONFIG_NET_SCH_TAPRIO is not set
+# CONFIG_NET_SCH_GRED is not set
+# CONFIG_NET_SCH_DSMARK is not set
+# CONFIG_NET_SCH_NETEM is not set
+# CONFIG_NET_SCH_DRR is not set
+# CONFIG_NET_SCH_MQPRIO is not set
+# CONFIG_NET_SCH_SKBPRIO is not set
+# CONFIG_NET_SCH_CHOKE is not set
+# CONFIG_NET_SCH_QFQ is not set
+# CONFIG_NET_SCH_CODEL is not set
+CONFIG_NET_SCH_FQ_CODEL=y
+# CONFIG_NET_SCH_CAKE is not set
+# CONFIG_NET_SCH_FQ is not set
+# CONFIG_NET_SCH_HHF is not set
+# CONFIG_NET_SCH_PIE is not set
+# CONFIG_NET_SCH_PLUG is not set
+# CONFIG_NET_SCH_DEFAULT is not set
+
+#
+# Classification
+#
+# CONFIG_NET_CLS_BASIC is not set
+# CONFIG_NET_CLS_TCINDEX is not set
+# CONFIG_NET_CLS_ROUTE4 is not set
+# CONFIG_NET_CLS_FW is not set
+# CONFIG_NET_CLS_U32 is not set
+# CONFIG_NET_CLS_RSVP is not set
+# CONFIG_NET_CLS_RSVP6 is not set
+# CONFIG_NET_CLS_FLOW is not set
+# CONFIG_NET_CLS_CGROUP is not set
+# CONFIG_NET_CLS_BPF is not set
+# CONFIG_NET_CLS_FLOWER is not set
+# CONFIG_NET_CLS_MATCHALL is not set
+# CONFIG_NET_EMATCH is not set
+# CONFIG_NET_CLS_ACT is not set
+CONFIG_NET_SCH_FIFO=y
+# CONFIG_DCB is not set
+# CONFIG_DNS_RESOLVER is not set
+# CONFIG_BATMAN_ADV is not set
+# CONFIG_OPENVSWITCH is not set
+# CONFIG_VSOCKETS is not set
+# CONFIG_NETLINK_DIAG is not set
+# CONFIG_MPLS is not set
+# CONFIG_NET_NSH is not set
+# CONFIG_HSR is not set
+# CONFIG_NET_SWITCHDEV is not set
+# CONFIG_NET_L3_MASTER_DEV is not set
+# CONFIG_NET_NCSI is not set
+# CONFIG_CGROUP_NET_PRIO is not set
+# CONFIG_CGROUP_NET_CLASSID is not set
+CONFIG_NET_RX_BUSY_POLL=y
+CONFIG_BQL=y
+CONFIG_BPF_JIT=y
+
+#
+# Network testing
+#
+# CONFIG_NET_PKTGEN is not set
+# end of Network testing
+# end of Networking options
+
+# CONFIG_HAMRADIO is not set
+# CONFIG_CAN is not set
+# CONFIG_BT is not set
+# CONFIG_AF_RXRPC is not set
+# CONFIG_AF_KCM is not set
+CONFIG_FIB_RULES=y
+CONFIG_WIRELESS=y
+CONFIG_WIRELESS_EXT=y
+CONFIG_WEXT_CORE=y
+CONFIG_WEXT_PROC=y
+CONFIG_WEXT_SPY=y
+CONFIG_WEXT_PRIV=y
+#CONFIG_CFG80211=y
+# CONFIG_NL80211_TESTMODE is not set
+# CONFIG_CFG80211_DEVELOPER_WARNINGS is not set
+# CONFIG_CFG80211_CERTIFICATION_ONUS is not set
+CONFIG_CFG80211_REQUIRE_SIGNED_REGDB=y
+CONFIG_CFG80211_USE_KERNEL_REGDB_KEYS=y
+CONFIG_CFG80211_DEFAULT_PS=y
+# CONFIG_CFG80211_DEBUGFS is not set
+CONFIG_CFG80211_CRDA_SUPPORT=y
+CONFIG_CFG80211_WEXT=y
+# CONFIG_LIB80211 is not set
+# CONFIG_LIB80211_CRYPT_WEP is not set
+# CONFIG_LIB80211_CRYPT_CCMP is not set
+# CONFIG_LIB80211_CRYPT_TKIP is not set
+#CONFIG_MAC80211=y
+CONFIG_MAC80211_HAS_RC=y
+CONFIG_MAC80211_RC_MINSTREL=y
+CONFIG_MAC80211_RC_DEFAULT_MINSTREL=y
+CONFIG_MAC80211_RC_DEFAULT="minstrel_ht"
+# CONFIG_MAC80211_MESH is not set
+# CONFIG_MAC80211_DEBUGFS is not set
+# CONFIG_MAC80211_MESSAGE_TRACING is not set
+# CONFIG_MAC80211_DEBUG_MENU is not set
+CONFIG_MAC80211_STA_HASH_MAX_SIZE=0
+# CONFIG_WIMAX is not set
+CONFIG_RFKILL=y
+# CONFIG_RFKILL_FULL is not set
+# CONFIG_NET_9P is not set
+# CONFIG_CAIF is not set
+# CONFIG_CEPH_LIB is not set
+# CONFIG_NFC is not set
+# CONFIG_PSAMPLE is not set
+# CONFIG_NET_IFE is not set
+# CONFIG_LWTUNNEL is not set
+CONFIG_DST_CACHE=y
+CONFIG_GRO_CELLS=y
+# CONFIG_FAILOVER is not set
+CONFIG_HAVE_CBPF_JIT=y
+
+#
+# Device Drivers
+#
+CONFIG_HAVE_PCI=y
+CONFIG_PCI=y
+CONFIG_PCI_DOMAINS=y
+# CONFIG_PCIEPORTBUS is not set
+# CONFIG_PCI_MSI is not set
+# CONFIG_PCI_QUIRKS is not set
+# CONFIG_PCI_DEBUG is not set
+# CONFIG_PCI_STUB is not set
+# CONFIG_PCI_DISABLE_COMMON_QUIRKS is not set
+# CONFIG_PCI_IOV is not set
+# CONFIG_PCI_PRI is not set
+# CONFIG_PCI_PASID is not set
+# CONFIG_HOTPLUG_PCI is not set
+
+#
+# PCI controller drivers
+#
+
+#
+# Cadence PCIe controllers support
+#
+# CONFIG_PCIE_CADENCE_HOST is not set
+# end of Cadence PCIe controllers support
+
+# CONFIG_PCI_FTPCI100 is not set
+# CONFIG_PCI_HOST_GENERIC is not set
+# CONFIG_PCIE_XILINX is not set
+
+#
+# DesignWare PCI Core Support
+#
+# end of DesignWare PCI Core Support
+# end of PCI controller drivers
+
+#
+# PCI Endpoint
+#
+# CONFIG_PCI_ENDPOINT is not set
+# end of PCI Endpoint
+
+#
+# PCI switch controller drivers
+#
+# CONFIG_PCI_SW_SWITCHTEC is not set
+# end of PCI switch controller drivers
+
+# CONFIG_PCCARD is not set
+# CONFIG_RAPIDIO is not set
+
+#
+# Generic Driver Options
+#
+# CONFIG_UEVENT_HELPER is not set
+# CONFIG_DEVTMPFS is not set
+CONFIG_STANDALONE=y
+CONFIG_PREVENT_FIRMWARE_BUILD=y
+
+#
+# Firmware loader
+#
+CONFIG_FW_LOADER=y
+CONFIG_EXTRA_FIRMWARE=""
+# CONFIG_FW_LOADER_USER_HELPER is not set
+# CONFIG_FW_LOADER_COMPRESS is not set
+# end of Firmware loader
+
+CONFIG_ALLOW_DEV_COREDUMP=y
+# CONFIG_DEBUG_DRIVER is not set
+# CONFIG_DEBUG_DEVRES is not set
+# CONFIG_DEBUG_TEST_DRIVER_REMOVE is not set
+# CONFIG_TEST_ASYNC_DRIVER_PROBE is not set
+CONFIG_GENERIC_CPU_AUTOPROBE=y
+CONFIG_REGMAP=y
+CONFIG_REGMAP_MMIO=y
+# end of Generic Driver Options
+
+#
+# Bus devices
+#
+# CONFIG_BRCMSTB_GISB_ARB is not set
+# CONFIG_MOXTET is not set
+# CONFIG_MIPS_CDMM is not set
+# end of Bus devices
+
+# CONFIG_CONNECTOR is not set
+# CONFIG_GNSS is not set
+CONFIG_MTD=y
+
+#
+# OpenWrt specific MTD options
+#
+CONFIG_MTD_ROOTFS_ROOT_DEV=y
+# CONFIG_MTD_SPLIT_FIRMWARE is not set
+CONFIG_MTD_SPLIT=y
+CONFIG_MTD_SPLIT_SUPPORT=y
+
+#
+# Rootfs partition parsers
+#
+CONFIG_MTD_SPLIT_SQUASHFS_ROOT=y
+
+#
+# Firmware partition parsers
+#
+# CONFIG_MTD_SPLIT_BCM_WFI_FW is not set
+# CONFIG_MTD_SPLIT_SEAMA_FW is not set
+# CONFIG_MTD_SPLIT_WRGG_FW is not set
+# CONFIG_MTD_SPLIT_UIMAGE_FW is not set
+# CONFIG_MTD_SPLIT_FIT_FW is not set
+# CONFIG_MTD_SPLIT_LZMA_FW is not set
+# CONFIG_MTD_SPLIT_TPLINK_FW is not set
+# CONFIG_MTD_SPLIT_TRX_FW is not set
+# CONFIG_MTD_SPLIT_BRNIMAGE_FW is not set
+# CONFIG_MTD_SPLIT_EVA_FW is not set
+# CONFIG_MTD_SPLIT_MINOR_FW is not set
+# CONFIG_MTD_SPLIT_JIMAGE_FW is not set
+# CONFIG_MTD_SPLIT_ELF_FW is not set
+# end of OpenWrt specific MTD options
+
+# CONFIG_MTD_TESTS is not set
+
+#
+# Partition parsers
+#
+# CONFIG_MTD_AR7_PARTS is not set
+# CONFIG_MTD_CMDLINE_PARTS is not set
+CONFIG_MTD_OF_PARTS=y
+# CONFIG_MTD_REDBOOT_PARTS is not set
+# CONFIG_MTD_ROUTERBOOT_PARTS is not set
+# end of Partition parsers
+
+#
+# User Modules And Translation Layers
+#
+# CONFIG_MTD_OOPS is not set
+CONFIG_MTD_PARTITIONED_MASTER=y
+
+#
+# RAM/ROM/Flash chip drivers
+#
+CONFIG_MTD_CFI=y
+CONFIG_MTD_JEDECPROBE=y
+CONFIG_MTD_GEN_PROBE=y
+# CONFIG_MTD_CFI_ADV_OPTIONS is not set
+CONFIG_MTD_MAP_BANK_WIDTH_1=y
+CONFIG_MTD_MAP_BANK_WIDTH_2=y
+CONFIG_MTD_MAP_BANK_WIDTH_4=y
+CONFIG_MTD_CFI_I1=y
+CONFIG_MTD_CFI_I2=y
+CONFIG_MTD_CFI_INTELEXT=y
+CONFIG_MTD_CFI_AMDSTD=y
+CONFIG_MTD_CFI_STAA=y
+CONFIG_MTD_CFI_UTIL=y
+# CONFIG_MTD_RAM is not set
+# CONFIG_MTD_ROM is not set
+# CONFIG_MTD_ABSENT is not set
+# end of RAM/ROM/Flash chip drivers
+
+#
+# Mapping drivers for chip access
+#
+CONFIG_MTD_COMPLEX_MAPPINGS=y
+CONFIG_MTD_PHYSMAP=y
+# CONFIG_MTD_PHYSMAP_COMPAT is not set
+CONFIG_MTD_PHYSMAP_OF=y
+# CONFIG_MTD_PHYSMAP_VERSATILE is not set
+# CONFIG_MTD_PHYSMAP_GEMINI is not set
+# CONFIG_MTD_PCI is not set
+# CONFIG_MTD_INTEL_VR_NOR is not set
+# CONFIG_MTD_PLATRAM is not set
+# end of Mapping drivers for chip access
+
+#
+# Self-contained MTD device drivers
+#
+# CONFIG_MTD_PMC551 is not set
+# CONFIG_MTD_DATAFLASH is not set
+# CONFIG_MTD_MCHP23K256 is not set
+# CONFIG_MTD_SST25L is not set
+# CONFIG_MTD_SLRAM is not set
+# CONFIG_MTD_PHRAM is not set
+# CONFIG_MTD_MTDRAM is not set
+
+#
+# Disk-On-Chip Device Drivers
+#
+# CONFIG_MTD_DOCG3 is not set
+# end of Self-contained MTD device drivers
+
+# CONFIG_MTD_ONENAND is not set
+# CONFIG_MTD_RAW_NAND is not set
+# CONFIG_MTD_SPI_NAND is not set
+
+#
+# LPDDR & LPDDR2 PCM memory drivers
+#
+# CONFIG_MTD_LPDDR is not set
+# end of LPDDR & LPDDR2 PCM memory drivers
+
+CONFIG_MTD_SPI_NOR=y
+CONFIG_MTD_SPI_NOR_USE_4K_SECTORS=y
+CONFIG_MTD_SPI_NOR_USE_4K_SECTORS_LIMIT=4096
+# CONFIG_SPI_MTK_QUADSPI is not set
+# CONFIG_MTD_UBI is not set
+# CONFIG_MTD_HYPERBUS is not set
+
+#
+# Composite MTD device drivers
+#
+# CONFIG_MTD_VIRT_CONCAT is not set
+# end of Composite MTD device drivers
+
+CONFIG_DTC=y
+CONFIG_OF=y
+# CONFIG_OF_UNITTEST is not set
+CONFIG_OF_FLATTREE=y
+CONFIG_OF_EARLY_FLATTREE=y
+CONFIG_OF_KOBJ=y
+CONFIG_OF_ADDRESS=y
+CONFIG_OF_IRQ=y
+CONFIG_OF_NET=y
+CONFIG_OF_MDIO=y
+CONFIG_OF_RESERVED_MEM=y
+# CONFIG_OF_OVERLAY is not set
+# CONFIG_PARPORT is not set
+
+#
+# NVME Support
+#
+# end of NVME Support
+
+#
+# Misc devices
+#
+# CONFIG_AD525X_DPOT is not set
+# CONFIG_DUMMY_IRQ is not set
+# CONFIG_PHANTOM is not set
+# CONFIG_TIFM_CORE is not set
+# CONFIG_ENCLOSURE_SERVICES is not set
+# CONFIG_HP_ILO is not set
+# CONFIG_PCH_PHUB is not set
+# CONFIG_LATTICE_ECP3_CONFIG is not set
+# CONFIG_SRAM is not set
+# CONFIG_PCI_ENDPOINT_TEST is not set
+# CONFIG_XILINX_SDFEC is not set
+# CONFIG_PVPANIC is not set
+# CONFIG_C2PORT is not set
+
+#
+# EEPROM support
+#
+# CONFIG_EEPROM_AT25 is not set
+CONFIG_EEPROM_93CX6=y
+# CONFIG_EEPROM_93XX46 is not set
+# end of EEPROM support
+
+# CONFIG_CB710_CORE is not set
+
+#
+# Texas Instruments shared transport line discipline
+#
+# end of Texas Instruments shared transport line discipline
+
+#
+# Altera FPGA firmware download module (requires I2C)
+#
+
+#
+# Intel MIC & related support
+#
+
+#
+# Intel MIC Bus Driver
+#
+
+#
+# SCIF Bus Driver
+#
+
+#
+# VOP Bus Driver
+#
+# CONFIG_VOP_BUS is not set
+
+#
+# Intel MIC Host Driver
+#
+
+#
+# Intel MIC Card Driver
+#
+
+#
+# SCIF Driver
+#
+
+#
+# Intel MIC Coprocessor State Management (COSM) Drivers
+#
+
+#
+# VOP Driver
+#
+# end of Intel MIC & related support
+
+# CONFIG_ECHO is not set
+# CONFIG_MISC_ALCOR_PCI is not set
+# CONFIG_MISC_RTSX_PCI is not set
+# CONFIG_HABANA_AI is not set
+# end of Misc devices
+
+CONFIG_HAVE_IDE=y
+
+#
+# SCSI device support
+#
+CONFIG_SCSI_MOD=y
+# end of SCSI device support
+
+# CONFIG_FUSION is not set
+
+#
+# IEEE 1394 (FireWire) support
+#
+# CONFIG_FIREWIRE is not set
+# CONFIG_FIREWIRE_NOSY is not set
+# end of IEEE 1394 (FireWire) support
+
+CONFIG_NETDEVICES=y
+CONFIG_MII=y
+CONFIG_NET_CORE=y
+# CONFIG_BONDING is not set
+# CONFIG_DUMMY is not set
+# CONFIG_EQUALIZER is not set
+# CONFIG_NET_TEAM is not set
+# CONFIG_MACVLAN is not set
+# CONFIG_IPVLAN is not set
+# CONFIG_VXLAN is not set
+# CONFIG_GENEVE is not set
+# CONFIG_GTP is not set
+# CONFIG_MACSEC is not set
+# CONFIG_NETCONSOLE is not set
+# CONFIG_TUN is not set
+# CONFIG_TUN_VNET_CROSS_LE is not set
+# CONFIG_VETH is not set
+# CONFIG_NLMON is not set
+# CONFIG_ARCNET is not set
+
+#
+# CAIF transport drivers
+#
+
+#
+# Distributed Switch Architecture drivers
+#
+# end of Distributed Switch Architecture drivers
+
+CONFIG_ETHERNET=y
+CONFIG_NET_VENDOR_3COM=y
+# CONFIG_VORTEX is not set
+# CONFIG_TYPHOON is not set
+CONFIG_NET_VENDOR_ADAPTEC=y
+# CONFIG_ADAPTEC_STARFIRE is not set
+CONFIG_NET_VENDOR_AGERE=y
+# CONFIG_ET131X is not set
+# CONFIG_NET_VENDOR_ALACRITECH is not set
+CONFIG_NET_VENDOR_ALTEON=y
+# CONFIG_ACENIC is not set
+# CONFIG_ALTERA_TSE is not set
+# CONFIG_NET_VENDOR_AMAZON is not set
+CONFIG_NET_VENDOR_AMD=y
+# CONFIG_AMD8111_ETH is not set
+# CONFIG_PCNET32 is not set
+# CONFIG_NET_VENDOR_AQUANTIA is not set
+# CONFIG_NET_VENDOR_ARC is not set
+CONFIG_NET_VENDOR_ATHEROS=y
+# CONFIG_ATL2 is not set
+# CONFIG_ATL1 is not set
+# CONFIG_ATL1E is not set
+# CONFIG_ATL1C is not set
+# CONFIG_ALX is not set
+# CONFIG_NET_VENDOR_AURORA is not set
+# CONFIG_NET_VENDOR_BROADCOM is not set
+CONFIG_NET_VENDOR_BROCADE=y
+# CONFIG_BNA is not set
+# CONFIG_NET_VENDOR_CADENCE is not set
+# CONFIG_NET_VENDOR_CAVIUM is not set
+CONFIG_NET_VENDOR_CHELSIO=y
+# CONFIG_CHELSIO_T1 is not set
+# CONFIG_CHELSIO_T3 is not set
+# CONFIG_CHELSIO_T4 is not set
+# CONFIG_CHELSIO_T4VF is not set
+CONFIG_NET_VENDOR_CISCO=y
+# CONFIG_ENIC is not set
+# CONFIG_NET_VENDOR_CORTINA is not set
+# CONFIG_DM9000 is not set
+# CONFIG_DNET is not set
+CONFIG_NET_VENDOR_DEC=y
+# CONFIG_NET_TULIP is not set
+CONFIG_NET_VENDOR_DLINK=y
+# CONFIG_DL2K is not set
+# CONFIG_SUNDANCE is not set
+CONFIG_NET_VENDOR_EMULEX=y
+# CONFIG_BE2NET is not set
+# CONFIG_NET_VENDOR_EZCHIP is not set
+# CONFIG_NET_VENDOR_GOOGLE is not set
+CONFIG_NET_VENDOR_HP=y
+# CONFIG_HP100 is not set
+# CONFIG_NET_VENDOR_HUAWEI is not set
+# CONFIG_NET_VENDOR_INTEL is not set
+# CONFIG_JME is not set
+CONFIG_NET_VENDOR_MARVELL=y
+# CONFIG_MVMDIO is not set
+# CONFIG_SKGE is not set
+# CONFIG_SKY2 is not set
+CONFIG_NET_VENDOR_MELLANOX=y
+# CONFIG_MLX4_EN is not set
+# CONFIG_MLX5_CORE is not set
+# CONFIG_MLXSW_CORE is not set
+# CONFIG_MLXFW is not set
+# CONFIG_NET_VENDOR_MICREL is not set
+# CONFIG_NET_VENDOR_MICROCHIP is not set
+# CONFIG_NET_VENDOR_MICROSEMI is not set
+CONFIG_NET_VENDOR_MYRI=y
+# CONFIG_MYRI10GE is not set
+# CONFIG_FEALNX is not set
+# CONFIG_NET_VENDOR_NATSEMI is not set
+CONFIG_NET_VENDOR_NETERION=y
+# CONFIG_S2IO is not set
+# CONFIG_VXGE is not set
+# CONFIG_NET_VENDOR_NETRONOME is not set
+# CONFIG_NET_VENDOR_NI is not set
+CONFIG_NET_VENDOR_NVIDIA=y
+# CONFIG_FORCEDETH is not set
+CONFIG_NET_VENDOR_OKI=y
+# CONFIG_ETHOC is not set
+CONFIG_NET_VENDOR_PACKET_ENGINES=y
+# CONFIG_HAMACHI is not set
+# CONFIG_YELLOWFIN is not set
+# CONFIG_NET_VENDOR_PENSANDO is not set
+CONFIG_NET_VENDOR_QLOGIC=y
+# CONFIG_QLA3XXX is not set
+# CONFIG_QLCNIC is not set
+# CONFIG_NETXEN_NIC is not set
+# CONFIG_QED is not set
+# CONFIG_NET_VENDOR_QUALCOMM is not set
+CONFIG_NET_VENDOR_RALINK=y
+CONFIG_NET_RALINK_SOC=y
+CONFIG_NET_RALINK_RT6855=y
+CONFIG_NET_RALINK_ESW_RT3050=y
+CONFIG_NET_VENDOR_RDC=y
+# CONFIG_R6040 is not set
+CONFIG_NET_VENDOR_REALTEK=y
+# CONFIG_8139CP is not set
+# CONFIG_8139TOO is not set
+# CONFIG_R8169 is not set
+# CONFIG_NET_VENDOR_RENESAS is not set
+# CONFIG_NET_VENDOR_ROCKER is not set
+# CONFIG_NET_VENDOR_SAMSUNG is not set
+# CONFIG_NET_VENDOR_SEEQ is not set
+# CONFIG_NET_VENDOR_SOLARFLARE is not set
+CONFIG_NET_VENDOR_SILAN=y
+# CONFIG_SC92031 is not set
+CONFIG_NET_VENDOR_SIS=y
+# CONFIG_SIS900 is not set
+# CONFIG_SIS190 is not set
+# CONFIG_NET_VENDOR_SMSC is not set
+# CONFIG_NET_VENDOR_SOCIONEXT is not set
+# CONFIG_NET_VENDOR_STMICRO is not set
+CONFIG_NET_VENDOR_SUN=y
+# CONFIG_HAPPYMEAL is not set
+# CONFIG_SUNGEM is not set
+# CONFIG_CASSINI is not set
+# CONFIG_NIU is not set
+# CONFIG_NET_VENDOR_SYNOPSYS is not set
+CONFIG_NET_VENDOR_TEHUTI=y
+# CONFIG_TEHUTI is not set
+CONFIG_NET_VENDOR_TI=y
+# CONFIG_TI_CPSW_PHY_SEL is not set
+# CONFIG_TLAN is not set
+CONFIG_NET_VENDOR_TOSHIBA=y
+# CONFIG_TC35815 is not set
+# CONFIG_NET_VENDOR_VIA is not set
+# CONFIG_NET_VENDOR_WIZNET is not set
+# CONFIG_NET_VENDOR_XILINX is not set
+# CONFIG_FDDI is not set
+# CONFIG_HIPPI is not set
+CONFIG_MDIO_DEVICE=y
+CONFIG_MDIO_BUS=y
+# CONFIG_MDIO_BCM_UNIMAC is not set
+# CONFIG_MDIO_BITBANG is not set
+# CONFIG_MDIO_BUS_MUX_MMIOREG is not set
+# CONFIG_MDIO_BUS_MUX_MULTIPLEXER is not set
+# CONFIG_MDIO_HISI_FEMAC is not set
+# CONFIG_MDIO_MSCC_MIIM is not set
+CONFIG_PHYLIB=y
+CONFIG_SWPHY=y
+
+#
+# Switch configuration API + drivers
+#
+CONFIG_SWCONFIG=y
+# CONFIG_ADM6996_PHY is not set
+# CONFIG_AR8216_PHY is not set
+# CONFIG_SWCONFIG_B53 is not set
+# CONFIG_IP17XX_PHY is not set
+# CONFIG_MVSWITCH_PHY is not set
+# CONFIG_PSB6970_PHY is not set
+# CONFIG_RTL8306_PHY is not set
+
+#
+# MII PHY device drivers
+#
+# CONFIG_ADIN_PHY is not set
+# CONFIG_AMD_PHY is not set
+# CONFIG_AQUANTIA_PHY is not set
+# CONFIG_AX88796B_PHY is not set
+# CONFIG_AT803X_PHY is not set
+# CONFIG_BCM7XXX_PHY is not set
+# CONFIG_BCM87XX_PHY is not set
+# CONFIG_BROADCOM_PHY is not set
+# CONFIG_BCM84881_PHY is not set
+# CONFIG_CICADA_PHY is not set
+# CONFIG_CORTINA_PHY is not set
+# CONFIG_DAVICOM_PHY is not set
+# CONFIG_DP83822_PHY is not set
+# CONFIG_DP83TC811_PHY is not set
+# CONFIG_DP83848_PHY is not set
+# CONFIG_DP83867_PHY is not set
+CONFIG_FIXED_PHY=y
+# CONFIG_ICPLUS_PHY is not set
+# CONFIG_INTEL_XWAY_PHY is not set
+# CONFIG_LSI_ET1011C_PHY is not set
+# CONFIG_LXT_PHY is not set
+# CONFIG_MARVELL_PHY is not set
+# CONFIG_MARVELL_10G_PHY is not set
+# CONFIG_MICREL_PHY is not set
+# CONFIG_MICROCHIP_PHY is not set
+# CONFIG_MICROCHIP_T1_PHY is not set
+# CONFIG_MICROSEMI_PHY is not set
+# CONFIG_NATIONAL_PHY is not set
+# CONFIG_QSEMI_PHY is not set
+# CONFIG_REALTEK_PHY is not set
+# CONFIG_RENESAS_PHY is not set
+# CONFIG_ROCKCHIP_PHY is not set
+# CONFIG_SMSC_PHY is not set
+# CONFIG_STE10XP is not set
+# CONFIG_TERANETICS_PHY is not set
+# CONFIG_VITESSE_PHY is not set
+# CONFIG_XILINX_GMII2RGMII is not set
+# CONFIG_MICREL_KS8995MA is not set
+CONFIG_PPP=m
+# CONFIG_PPP_BSDCOMP is not set
+# CONFIG_PPP_DEFLATE is not set
+CONFIG_PPP_FILTER=y
+# CONFIG_PPP_MPPE is not set
+CONFIG_PPP_MULTILINK=y
+CONFIG_PPPOE=m
+CONFIG_PPP_ASYNC=m
+# CONFIG_PPP_SYNC_TTY is not set
+# CONFIG_SLIP is not set
+CONFIG_SLHC=m
+
+#
+# Host-side USB support is needed for USB Network Adapter support
+#
+CONFIG_WLAN=y
+# CONFIG_WIRELESS_WDS is not set
+# CONFIG_WLAN_VENDOR_ADMTEK is not set
+# CONFIG_WLAN_VENDOR_ATH is not set
+# CONFIG_WLAN_VENDOR_ATMEL is not set
+# CONFIG_WLAN_VENDOR_BROADCOM is not set
+# CONFIG_WLAN_VENDOR_CISCO is not set
+# CONFIG_WLAN_VENDOR_INTEL is not set
+# CONFIG_WLAN_VENDOR_INTERSIL is not set
+# CONFIG_WLAN_VENDOR_MARVELL is not set
+# CONFIG_WLAN_VENDOR_MEDIATEK is not set
+CONFIG_WLAN_VENDOR_RALINK=y
+#CONFIG_RT2X00=y
+# CONFIG_RT2400PCI is not set
+# CONFIG_RT2500PCI is not set
+# CONFIG_RT61PCI is not set
+CONFIG_RT2800PCI=y
+CONFIG_RT2800PCI_RT33XX=y
+CONFIG_RT2800PCI_RT35XX=y
+CONFIG_RT2800PCI_RT53XX=y
+CONFIG_RT2800PCI_RT3290=y
+CONFIG_RT2800_LIB=y
+CONFIG_RT2800_LIB_MMIO=y
+CONFIG_RT2X00_LIB_MMIO=y
+CONFIG_RT2X00_LIB_PCI=y
+CONFIG_RT2X00_LIB=y
+CONFIG_RT2X00_LIB_FIRMWARE=y
+CONFIG_RT2X00_LIB_CRYPTO=y
+# CONFIG_RT2X00_DEBUG is not set
+# CONFIG_WLAN_VENDOR_REALTEK is not set
+# CONFIG_WLAN_VENDOR_RSI is not set
+# CONFIG_WLAN_VENDOR_ST is not set
+# CONFIG_WLAN_VENDOR_TI is not set
+# CONFIG_WLAN_VENDOR_ZYDAS is not set
+# CONFIG_WLAN_VENDOR_QUANTENNA is not set
+# CONFIG_MAC80211_HWSIM is not set
+# CONFIG_VIRT_WIFI is not set
+
+#
+# Enable WiMAX (Networking options) to see the WiMAX drivers
+#
+# CONFIG_WAN is not set
+# CONFIG_VMXNET3 is not set
+# CONFIG_NETDEVSIM is not set
+# CONFIG_NET_FAILOVER is not set
+# CONFIG_ISDN is not set
+
+#
+# Input device support
+#
+# CONFIG_INPUT is not set
+
+#
+# Hardware I/O ports
+#
+# CONFIG_SERIO is not set
+# CONFIG_GAMEPORT is not set
+# end of Hardware I/O ports
+# end of Input device support
+
+#
+# Character devices
+#
+CONFIG_TTY=y
+# CONFIG_VT is not set
+CONFIG_UNIX98_PTYS=y
+CONFIG_LEGACY_PTYS=y
+CONFIG_LEGACY_PTY_COUNT=8
+# CONFIG_SERIAL_NONSTANDARD is not set
+# CONFIG_NOZOMI is not set
+# CONFIG_N_GSM is not set
+# CONFIG_TRACE_SINK is not set
+# CONFIG_NULL_TTY is not set
+CONFIG_LDISC_AUTOLOAD=y
+# CONFIG_DEVMEM is not set
+# CONFIG_DEVKMEM is not set
+
+#
+# Serial drivers
+#
+CONFIG_SERIAL_EARLYCON=y
+CONFIG_SERIAL_8250=y
+# CONFIG_SERIAL_8250_DEPRECATED_OPTIONS is not set
+# CONFIG_SERIAL_8250_FINTEK is not set
+CONFIG_SERIAL_8250_CONSOLE=y
+CONFIG_SERIAL_8250_DMA=y
+CONFIG_SERIAL_8250_PCI=y
+CONFIG_SERIAL_8250_EXAR=y
+CONFIG_SERIAL_8250_NR_UARTS=1
+CONFIG_SERIAL_8250_RUNTIME_UARTS=1
+# CONFIG_SERIAL_8250_EXTENDED is not set
+# CONFIG_SERIAL_8250_ASPEED_VUART is not set
+# CONFIG_SERIAL_8250_DW is not set
+# CONFIG_SERIAL_8250_RT288X is not set
+# CONFIG_SERIAL_8250_INGENIC is not set
+CONFIG_SERIAL_OF_PLATFORM=y
+
+#
+# Non-8250 serial port support
+#
+# CONFIG_SERIAL_MAX3100 is not set
+# CONFIG_SERIAL_MAX310X is not set
+# CONFIG_SERIAL_UARTLITE is not set
+CONFIG_SERIAL_CORE=y
+CONFIG_SERIAL_CORE_CONSOLE=y
+# CONFIG_SERIAL_JSM is not set
+# CONFIG_SERIAL_SIFIVE is not set
+# CONFIG_SERIAL_SCCNXP is not set
+# CONFIG_SERIAL_SC16IS7XX is not set
+# CONFIG_SERIAL_BCM63XX is not set
+# CONFIG_SERIAL_ALTERA_JTAGUART is not set
+# CONFIG_SERIAL_ALTERA_UART is not set
+# CONFIG_SERIAL_PCH_UART is not set
+# CONFIG_SERIAL_XILINX_PS_UART is not set
+# CONFIG_SERIAL_ARC is not set
+# CONFIG_SERIAL_RP2 is not set
+# CONFIG_SERIAL_FSL_LPUART is not set
+# CONFIG_SERIAL_FSL_LINFLEXUART is not set
+# CONFIG_SERIAL_CONEXANT_DIGICOLOR is not set
+# end of Serial drivers
+
+# CONFIG_SERIAL_DEV_BUS is not set
+# CONFIG_TTY_PRINTK is not set
+# CONFIG_IPMI_HANDLER is not set
+# CONFIG_HW_RANDOM is not set
+# CONFIG_APPLICOM is not set
+# CONFIG_TCG_TPM is not set
+CONFIG_DEVPORT=y
+# CONFIG_XILLYBUS is not set
+# end of Character devices
+
+# CONFIG_RANDOM_TRUST_BOOTLOADER is not set
+
+#
+# I2C support
+#
+# CONFIG_I2C is not set
+# end of I2C support
+
+# CONFIG_I3C is not set
+CONFIG_SPI=y
+CONFIG_SPI_DEBUG=y
+CONFIG_SPI_MASTER=y
+CONFIG_SPI_MEM=y
+
+#
+# SPI Master Controller Drivers
+#
+# CONFIG_SPI_ALTERA is not set
+# CONFIG_SPI_AXI_SPI_ENGINE is not set
+# CONFIG_SPI_BITBANG is not set
+# CONFIG_SPI_CADENCE is not set
+# CONFIG_SPI_DESIGNWARE is not set
+# CONFIG_SPI_NXP_FLEXSPI is not set
+# CONFIG_SPI_IMG_SPFI is not set
+# CONFIG_SPI_FSL_SPI is not set
+CONFIG_SPI_MT7621=y
+# CONFIG_SPI_PXA2XX is not set
+# CONFIG_SPI_ROCKCHIP is not set
+# CONFIG_SPI_RT2880 is not set
+# CONFIG_SPI_SIFIVE is not set
+# CONFIG_SPI_MXIC is not set
+# CONFIG_SPI_TOPCLIFF_PCH is not set
+# CONFIG_SPI_XILINX is not set
+# CONFIG_SPI_ZYNQMP_GQSPI is not set
+
+#
+# SPI Protocol Masters
+#
+# CONFIG_SPI_SPIDEV is not set
+# CONFIG_SPI_LOOPBACK_TEST is not set
+# CONFIG_SPI_TLE62X0 is not set
+# CONFIG_SPI_SLAVE is not set
+# CONFIG_SPMI is not set
+# CONFIG_HSI is not set
+# CONFIG_PPS is not set
+
+#
+# PTP clock support
+#
+# CONFIG_PTP_1588_CLOCK is not set
+
+#
+# Enable PHYLIB and NETWORK_PHY_TIMESTAMPING to see the additional clocks.
+#
+# end of PTP clock support
+
+# CONFIG_PINCTRL is not set
+# CONFIG_GPIOLIB is not set
+# CONFIG_W1 is not set
+# CONFIG_POWER_AVS is not set
+# CONFIG_POWER_RESET is not set
+# CONFIG_POWER_SUPPLY is not set
+# CONFIG_HWMON is not set
+# CONFIG_THERMAL is not set
+CONFIG_WATCHDOG=y
+CONFIG_WATCHDOG_CORE=y
+# CONFIG_WATCHDOG_NOWAYOUT is not set
+CONFIG_WATCHDOG_HANDLE_BOOT_ENABLED=y
+CONFIG_WATCHDOG_OPEN_TIMEOUT=0
+# CONFIG_WATCHDOG_SYSFS is not set
+
+#
+# Watchdog Pretimeout Governors
+#
+# CONFIG_WATCHDOG_PRETIMEOUT_GOV is not set
+
+#
+# Watchdog Device Drivers
+#
+# CONFIG_SOFT_WATCHDOG is not set
+# CONFIG_XILINX_WATCHDOG is not set
+# CONFIG_CADENCE_WATCHDOG is not set
+# CONFIG_DW_WATCHDOG is not set
+# CONFIG_MAX63XX_WATCHDOG is not set
+# CONFIG_ALIM7101_WDT is not set
+# CONFIG_I6300ESB_WDT is not set
+# CONFIG_IMGPDC_WDT is not set
+CONFIG_RALINK_WDT=y
+CONFIG_RT6855_WDT=y
+
+#
+# PCI-based Watchdog Cards
+#
+# CONFIG_PCIPCWATCHDOG is not set
+# CONFIG_WDTPCI is not set
+CONFIG_SSB_POSSIBLE=y
+# CONFIG_SSB is not set
+CONFIG_BCMA_POSSIBLE=y
+# CONFIG_BCMA is not set
+
+#
+# Multifunction device drivers
+#
+# CONFIG_MFD_ATMEL_FLEXCOM is not set
+# CONFIG_MFD_ATMEL_HLCDC is not set
+# CONFIG_MFD_MADERA is not set
+# CONFIG_MFD_DA9052_SPI is not set
+# CONFIG_MFD_MC13XXX_SPI is not set
+# CONFIG_MFD_HI6421_PMIC is not set
+# CONFIG_HTC_PASIC3 is not set
+# CONFIG_LPC_ICH is not set
+# CONFIG_LPC_SCH is not set
+# CONFIG_MFD_JANZ_CMODIO is not set
+# CONFIG_MFD_KEMPLD is not set
+# CONFIG_MFD_MT6397 is not set
+# CONFIG_EZX_PCAP is not set
+# CONFIG_MFD_CPCAP is not set
+# CONFIG_MFD_RDC321X is not set
+# CONFIG_MFD_SM501 is not set
+# CONFIG_ABX500_CORE is not set
+# CONFIG_MFD_STMPE is not set
+CONFIG_MFD_SYSCON=y
+# CONFIG_MFD_TI_AM335X_TSCADC is not set
+# CONFIG_MFD_TPS65912_SPI is not set
+# CONFIG_MFD_TQMX86 is not set
+# CONFIG_MFD_VX855 is not set
+# CONFIG_MFD_ARIZONA_SPI is not set
+# CONFIG_MFD_WM831X_SPI is not set
+# end of Multifunction device drivers
+
+# CONFIG_REGULATOR is not set
+# CONFIG_MEDIA_SUPPORT is not set
+
+#
+# Graphics support
+#
+CONFIG_VGA_ARB=y
+CONFIG_VGA_ARB_MAX_GPUS=16
+# CONFIG_DRM is not set
+# CONFIG_DRM_DP_CEC is not set
+
+#
+# ARM devices
+#
+# end of ARM devices
+
+#
+# ACP (Audio CoProcessor) Configuration
+#
+# end of ACP (Audio CoProcessor) Configuration
+
+#
+# Frame buffer Devices
+#
+# CONFIG_FB is not set
+# end of Frame buffer Devices
+
+#
+# Backlight & LCD device support
+#
+# CONFIG_LCD_CLASS_DEVICE is not set
+# CONFIG_BACKLIGHT_CLASS_DEVICE is not set
+# end of Backlight & LCD device support
+# end of Graphics support
+
+# CONFIG_SOUND is not set
+CONFIG_USB_OHCI_LITTLE_ENDIAN=y
+# CONFIG_USB_SUPPORT is not set
+# CONFIG_MMC is not set
+# CONFIG_MEMSTICK is not set
+# CONFIG_NEW_LEDS is not set
+# CONFIG_ACCESSIBILITY is not set
+# CONFIG_INFINIBAND is not set
+CONFIG_RTC_LIB=y
+# CONFIG_RTC_CLASS is not set
+CONFIG_DMADEVICES=y
+# CONFIG_DMADEVICES_DEBUG is not set
+
+#
+# DMA Devices
+#
+CONFIG_DMA_ENGINE=y
+CONFIG_DMA_VIRTUAL_CHANNELS=y
+CONFIG_DMA_OF=y
+# CONFIG_ALTERA_MSGDMA is not set
+# CONFIG_DMA_JZ4780 is not set
+# CONFIG_DW_AXI_DMAC is not set
+# CONFIG_FSL_EDMA is not set
+# CONFIG_IMG_MDC_DMA is not set
+# CONFIG_INTEL_IDMA64 is not set
+# CONFIG_QCOM_HIDMA_MGMT is not set
+# CONFIG_QCOM_HIDMA is not set
+# CONFIG_DW_DMAC is not set
+# CONFIG_DW_DMAC_PCI is not set
+
+#
+# DMA Clients
+#
+# CONFIG_ASYNC_TX_DMA is not set
+# CONFIG_DMATEST is not set
+
+#
+# DMABUF options
+#
+# CONFIG_SYNC_FILE is not set
+# end of DMABUF options
+
+# CONFIG_AUXDISPLAY is not set
+# CONFIG_UIO is not set
+# CONFIG_VIRT_DRIVERS is not set
+# CONFIG_VIRTIO_MENU is not set
+
+#
+# Microsoft Hyper-V guest support
+#
+# end of Microsoft Hyper-V guest support
+
+# CONFIG_GREYBUS is not set
+CONFIG_STAGING=y
+# CONFIG_COMEDI is not set
+# CONFIG_RTLLIB is not set
+# CONFIG_VT6655 is not set
+
+#
+# Speakup console speech
+#
+# end of Speakup console speech
+
+# CONFIG_STAGING_MEDIA is not set
+
+#
+# Android
+#
+# end of Android
+
+# CONFIG_STAGING_BOARD is not set
+# CONFIG_GS_FPGABOOT is not set
+# CONFIG_UNISYSSPAR is not set
+# CONFIG_WILC1000_SPI is not set
+# CONFIG_PI433 is not set
+# CONFIG_PCI_MT7621 is not set
+# CONFIG_PCI_MT7621_PHY is not set
+# CONFIG_PINCTRL_RT2880 is not set
+CONFIG_DMA_RALINK=y
+
+#
+# Gasket devices
+#
+# end of Gasket devices
+
+# CONFIG_XIL_AXIS_FIFO is not set
+# CONFIG_FIELDBUS_DEV is not set
+# CONFIG_UWB is not set
+# CONFIG_QLGE is not set
+CONFIG_MIPS_PLATFORM_DEVICES=y
+# CONFIG_GOLDFISH is not set
+# CONFIG_MIKROTIK is not set
+CONFIG_CLKDEV_LOOKUP=y
+# CONFIG_HWSPINLOCK is not set
+
+#
+# Clock Source drivers
+#
+# end of Clock Source drivers
+
+# CONFIG_MAILBOX is not set
+# CONFIG_IOMMU_SUPPORT is not set
+
+#
+# Remoteproc drivers
+#
+# CONFIG_REMOTEPROC is not set
+# end of Remoteproc drivers
+
+#
+# Rpmsg drivers
+#
+# CONFIG_RPMSG_VIRTIO is not set
+# end of Rpmsg drivers
+
+# CONFIG_SOUNDWIRE is not set
+
+#
+# SOC (System On Chip) specific Drivers
+#
+
+#
+# Amlogic SoC drivers
+#
+# end of Amlogic SoC drivers
+
+#
+# Aspeed SoC drivers
+#
+# end of Aspeed SoC drivers
+
+#
+# Broadcom SoC drivers
+#
+# end of Broadcom SoC drivers
+
+#
+# NXP/Freescale QorIQ SoC drivers
+#
+# end of NXP/Freescale QorIQ SoC drivers
+
+#
+# i.MX SoC drivers
+#
+# end of i.MX SoC drivers
+
+#
+# Qualcomm SoC drivers
+#
+# end of Qualcomm SoC drivers
+
+# CONFIG_SOC_TI is not set
+
+#
+# Xilinx SoC drivers
+#
+# CONFIG_XILINX_VCU is not set
+# end of Xilinx SoC drivers
+# end of SOC (System On Chip) specific Drivers
+
+# CONFIG_PM_DEVFREQ is not set
+# CONFIG_EXTCON is not set
+# CONFIG_MEMORY is not set
+# CONFIG_IIO is not set
+# CONFIG_NTB is not set
+# CONFIG_VME_BUS is not set
+# CONFIG_PWM is not set
+
+#
+# IRQ chip support
+#
+CONFIG_IRQCHIP=y
+# CONFIG_AL_FIC is not set
+CONFIG_IRQ_MIPS_CPU=y
+# CONFIG_INGENIC_TCU_IRQ is not set
+# end of IRQ chip support
+
+# CONFIG_IPACK_BUS is not set
+CONFIG_ARCH_HAS_RESET_CONTROLLER=y
+CONFIG_RESET_CONTROLLER=y
+# CONFIG_RESET_TI_SYSCON is not set
+
+#
+# PHY Subsystem
+#
+# CONFIG_GENERIC_PHY is not set
+# CONFIG_BCM_KONA_USB2_PHY is not set
+# CONFIG_PHY_CADENCE_DP is not set
+# CONFIG_PHY_CADENCE_DPHY is not set
+# CONFIG_PHY_CADENCE_SIERRA is not set
+# CONFIG_PHY_FSL_IMX8MQ_USB is not set
+# CONFIG_PHY_MIXEL_MIPI_DPHY is not set
+# CONFIG_PHY_PXA_28NM_HSIC is not set
+# CONFIG_PHY_PXA_28NM_USB2 is not set
+# CONFIG_PHY_OCELOT_SERDES is not set
+# CONFIG_PHY_RALINK_USB is not set
+# end of PHY Subsystem
+
+# CONFIG_POWERCAP is not set
+# CONFIG_MCB is not set
+# CONFIG_RAS is not set
+
+#
+# Android
+#
+# CONFIG_ANDROID is not set
+# end of Android
+
+# CONFIG_DAX is not set
+# CONFIG_NVMEM is not set
+
+#
+# HW tracing support
+#
+# CONFIG_STM is not set
+# CONFIG_INTEL_TH is not set
+# end of HW tracing support
+
+# CONFIG_FPGA is not set
+# CONFIG_FSI is not set
+# CONFIG_SIOX is not set
+# CONFIG_SLIMBUS is not set
+# CONFIG_INTERCONNECT is not set
+# CONFIG_COUNTER is not set
+# end of Device Drivers
+
+#
+# File systems
+#
+# CONFIG_VALIDATE_FS_PARSER is not set
+CONFIG_EXPORTFS=y
+# CONFIG_EXPORTFS_BLOCK_OPS is not set
+# CONFIG_FILE_LOCKING is not set
+# CONFIG_FS_ENCRYPTION is not set
+# CONFIG_FS_VERITY is not set
+CONFIG_FSNOTIFY=y
+# CONFIG_DNOTIFY is not set
+# CONFIG_INOTIFY_USER is not set
+CONFIG_FANOTIFY=y
+# CONFIG_QUOTA is not set
+# CONFIG_AUTOFS4_FS is not set
+# CONFIG_AUTOFS_FS is not set
+# CONFIG_FUSE_FS is not set
+# CONFIG_OVERLAY_FS is not set
+
+#
+# Caches
+#
+# CONFIG_FSCACHE is not set
+# end of Caches
+
+#
+# Pseudo filesystems
+#
+CONFIG_PROC_FS=y
+# CONFIG_PROC_KCORE is not set
+CONFIG_PROC_SYSCTL=y
+# CONFIG_PROC_PAGE_MONITOR is not set
+# CONFIG_PROC_CHILDREN is not set
+CONFIG_PROC_STRIPPED=y
+CONFIG_KERNFS=y
+CONFIG_SYSFS=y
+CONFIG_TMPFS=y
+# CONFIG_TMPFS_POSIX_ACL is not set
+# CONFIG_TMPFS_XATTR is not set
+CONFIG_MEMFD_CREATE=y
+# CONFIG_CONFIGFS_FS is not set
+# end of Pseudo filesystems
+
+# CONFIG_MISC_FILESYSTEMS is not set
+CONFIG_NETWORK_FILESYSTEMS=y
+# CONFIG_CEPH_FS is not set
+# CONFIG_CIFS is not set
+# CONFIG_CODA_FS is not set
+# CONFIG_AFS_FS is not set
+CONFIG_NLS=y
+CONFIG_NLS_DEFAULT="utf8"
+CONFIG_NLS_CODEPAGE_437=y
+# CONFIG_NLS_CODEPAGE_737 is not set
+# CONFIG_NLS_CODEPAGE_775 is not set
+# CONFIG_NLS_CODEPAGE_850 is not set
+# CONFIG_NLS_CODEPAGE_852 is not set
+# CONFIG_NLS_CODEPAGE_855 is not set
+# CONFIG_NLS_CODEPAGE_857 is not set
+# CONFIG_NLS_CODEPAGE_860 is not set
+# CONFIG_NLS_CODEPAGE_861 is not set
+# CONFIG_NLS_CODEPAGE_862 is not set
+# CONFIG_NLS_CODEPAGE_863 is not set
+# CONFIG_NLS_CODEPAGE_864 is not set
+# CONFIG_NLS_CODEPAGE_865 is not set
+# CONFIG_NLS_CODEPAGE_866 is not set
+# CONFIG_NLS_CODEPAGE_869 is not set
+# CONFIG_NLS_CODEPAGE_936 is not set
+# CONFIG_NLS_CODEPAGE_950 is not set
+# CONFIG_NLS_CODEPAGE_932 is not set
+# CONFIG_NLS_CODEPAGE_949 is not set
+# CONFIG_NLS_CODEPAGE_874 is not set
+# CONFIG_NLS_ISO8859_8 is not set
+# CONFIG_NLS_CODEPAGE_1250 is not set
+# CONFIG_NLS_CODEPAGE_1251 is not set
+CONFIG_NLS_ASCII=y
+# CONFIG_NLS_ISO8859_1 is not set
+# CONFIG_NLS_ISO8859_2 is not set
+# CONFIG_NLS_ISO8859_3 is not set
+# CONFIG_NLS_ISO8859_4 is not set
+# CONFIG_NLS_ISO8859_5 is not set
+# CONFIG_NLS_ISO8859_6 is not set
+# CONFIG_NLS_ISO8859_7 is not set
+# CONFIG_NLS_ISO8859_9 is not set
+# CONFIG_NLS_ISO8859_13 is not set
+# CONFIG_NLS_ISO8859_14 is not set
+# CONFIG_NLS_ISO8859_15 is not set
+# CONFIG_NLS_KOI8_R is not set
+# CONFIG_NLS_KOI8_U is not set
+# CONFIG_NLS_MAC_ROMAN is not set
+# CONFIG_NLS_MAC_CELTIC is not set
+# CONFIG_NLS_MAC_CENTEURO is not set
+# CONFIG_NLS_MAC_CROATIAN is not set
+# CONFIG_NLS_MAC_CYRILLIC is not set
+# CONFIG_NLS_MAC_GAELIC is not set
+# CONFIG_NLS_MAC_GREEK is not set
+# CONFIG_NLS_MAC_ICELAND is not set
+# CONFIG_NLS_MAC_INUIT is not set
+# CONFIG_NLS_MAC_ROMANIAN is not set
+# CONFIG_NLS_MAC_TURKISH is not set
+CONFIG_NLS_UTF8=y
+# CONFIG_UNICODE is not set
+# end of File systems
+
+#
+# Security options
+#
+CONFIG_KEYS=y
+# CONFIG_KEYS_REQUEST_CACHE is not set
+# CONFIG_PERSISTENT_KEYRINGS is not set
+# CONFIG_BIG_KEYS is not set
+# CONFIG_ENCRYPTED_KEYS is not set
+# CONFIG_KEY_DH_OPERATIONS is not set
+# CONFIG_SECURITY_DMESG_RESTRICT is not set
+# CONFIG_SECURITY is not set
+# CONFIG_SECURITYFS is not set
+CONFIG_HAVE_HARDENED_USERCOPY_ALLOCATOR=y
+# CONFIG_HARDENED_USERCOPY is not set
+# CONFIG_STATIC_USERMODEHELPER is not set
+CONFIG_DEFAULT_SECURITY_DAC=y
+CONFIG_LSM="lockdown,yama,loadpin,safesetid,integrity,bpf"
+
+#
+# Kernel hardening options
+#
+
+#
+# Memory initialization
+#
+CONFIG_INIT_STACK_NONE=y
+# CONFIG_INIT_ON_ALLOC_DEFAULT_ON is not set
+# CONFIG_INIT_ON_FREE_DEFAULT_ON is not set
+# end of Memory initialization
+# end of Kernel hardening options
+# end of Security options
+
+CONFIG_CRYPTO=y
+
+#
+# Crypto core or helper
+#
+CONFIG_CRYPTO_ALGAPI=y
+CONFIG_CRYPTO_ALGAPI2=y
+CONFIG_CRYPTO_AEAD=y
+CONFIG_CRYPTO_AEAD2=y
+CONFIG_CRYPTO_BLKCIPHER=y
+CONFIG_CRYPTO_BLKCIPHER2=y
+CONFIG_CRYPTO_HASH=y
+CONFIG_CRYPTO_HASH2=y
+CONFIG_CRYPTO_RNG=y
+CONFIG_CRYPTO_RNG2=y
+CONFIG_CRYPTO_RNG_DEFAULT=y
+CONFIG_CRYPTO_AKCIPHER2=y
+CONFIG_CRYPTO_AKCIPHER=y
+CONFIG_CRYPTO_MANAGER=y
+CONFIG_CRYPTO_MANAGER2=y
+# CONFIG_CRYPTO_USER is not set
+CONFIG_CRYPTO_MANAGER_DISABLE_TESTS=y
+CONFIG_CRYPTO_GF128MUL=y
+CONFIG_CRYPTO_NULL=y
+CONFIG_CRYPTO_NULL2=y
+# CONFIG_CRYPTO_CRYPTD is not set
+# CONFIG_CRYPTO_AUTHENC is not set
+# CONFIG_CRYPTO_TEST is not set
+
+#
+# Public-key cryptography
+#
+CONFIG_CRYPTO_RSA=y
+# CONFIG_CRYPTO_DH is not set
+# CONFIG_CRYPTO_ECDH is not set
+# CONFIG_CRYPTO_ECRDSA is not set
+
+#
+# Authenticated Encryption with Associated Data
+#
+CONFIG_CRYPTO_CCM=y
+CONFIG_CRYPTO_GCM=y
+# CONFIG_CRYPTO_CHACHA20POLY1305 is not set
+# CONFIG_CRYPTO_AEGIS128 is not set
+CONFIG_CRYPTO_SEQIV=y
+# CONFIG_CRYPTO_ECHAINIV is not set
+
+#
+# Block modes
+#
+# CONFIG_CRYPTO_CBC is not set
+# CONFIG_CRYPTO_CFB is not set
+CONFIG_CRYPTO_CTR=y
+# CONFIG_CRYPTO_CTS is not set
+# CONFIG_CRYPTO_ECB is not set
+# CONFIG_CRYPTO_LRW is not set
+# CONFIG_CRYPTO_OFB is not set
+# CONFIG_CRYPTO_PCBC is not set
+# CONFIG_CRYPTO_XTS is not set
+# CONFIG_CRYPTO_KEYWRAP is not set
+# CONFIG_CRYPTO_ADIANTUM is not set
+# CONFIG_CRYPTO_ESSIV is not set
+
+#
+# Hash modes
+#
+CONFIG_CRYPTO_CMAC=y
+CONFIG_CRYPTO_HMAC=y
+# CONFIG_CRYPTO_XCBC is not set
+# CONFIG_CRYPTO_VMAC is not set
+
+#
+# Digest
+#
+# CONFIG_CRYPTO_CRC32C is not set
+# CONFIG_CRYPTO_CRC32 is not set
+# CONFIG_CRYPTO_XXHASH is not set
+# CONFIG_CRYPTO_CRCT10DIF is not set
+CONFIG_CRYPTO_GHASH=y
+# CONFIG_CRYPTO_POLY1305 is not set
+# CONFIG_CRYPTO_MD4 is not set
+# CONFIG_CRYPTO_MD5 is not set
+# CONFIG_CRYPTO_MICHAEL_MIC is not set
+# CONFIG_CRYPTO_RMD128 is not set
+# CONFIG_CRYPTO_RMD160 is not set
+# CONFIG_CRYPTO_RMD256 is not set
+# CONFIG_CRYPTO_RMD320 is not set
+# CONFIG_CRYPTO_SHA1 is not set
+CONFIG_CRYPTO_LIB_SHA256=y
+CONFIG_CRYPTO_SHA256=y
+# CONFIG_CRYPTO_SHA512 is not set
+# CONFIG_CRYPTO_SHA3 is not set
+# CONFIG_CRYPTO_SM3 is not set
+# CONFIG_CRYPTO_STREEBOG is not set
+# CONFIG_CRYPTO_TGR192 is not set
+# CONFIG_CRYPTO_WP512 is not set
+
+#
+# Ciphers
+#
+CONFIG_CRYPTO_LIB_AES=y
+CONFIG_CRYPTO_AES=y
+# CONFIG_CRYPTO_AES_TI is not set
+# CONFIG_CRYPTO_ANUBIS is not set
+CONFIG_CRYPTO_LIB_ARC4=y
+# CONFIG_CRYPTO_ARC4 is not set
+# CONFIG_CRYPTO_BLOWFISH is not set
+# CONFIG_CRYPTO_CAMELLIA is not set
+# CONFIG_CRYPTO_CAST5 is not set
+# CONFIG_CRYPTO_CAST6 is not set
+# CONFIG_CRYPTO_DES is not set
+# CONFIG_CRYPTO_FCRYPT is not set
+# CONFIG_CRYPTO_KHAZAD is not set
+# CONFIG_CRYPTO_SALSA20 is not set
+# CONFIG_CRYPTO_CHACHA20 is not set
+# CONFIG_CRYPTO_SEED is not set
+# CONFIG_CRYPTO_SERPENT is not set
+# CONFIG_CRYPTO_SM4 is not set
+# CONFIG_CRYPTO_TEA is not set
+# CONFIG_CRYPTO_TWOFISH is not set
+
+#
+# Compression
+#
+# CONFIG_CRYPTO_DEFLATE is not set
+# CONFIG_CRYPTO_LZO is not set
+# CONFIG_CRYPTO_842 is not set
+# CONFIG_CRYPTO_LZ4 is not set
+# CONFIG_CRYPTO_LZ4HC is not set
+# CONFIG_CRYPTO_ZSTD is not set
+
+#
+# Random Number Generation
+#
+# CONFIG_CRYPTO_ANSI_CPRNG is not set
+CONFIG_CRYPTO_DRBG_MENU=y
+CONFIG_CRYPTO_DRBG_HMAC=y
+# CONFIG_CRYPTO_DRBG_HASH is not set
+# CONFIG_CRYPTO_DRBG_CTR is not set
+CONFIG_CRYPTO_DRBG=y
+CONFIG_CRYPTO_JITTERENTROPY=y
+# CONFIG_CRYPTO_USER_API_HASH is not set
+# CONFIG_CRYPTO_USER_API_SKCIPHER is not set
+# CONFIG_CRYPTO_USER_API_RNG is not set
+# CONFIG_CRYPTO_USER_API_AEAD is not set
+CONFIG_CRYPTO_HASH_INFO=y
+CONFIG_CRYPTO_HW=y
+# CONFIG_CRYPTO_DEV_HIFN_795X is not set
+# CONFIG_CRYPTO_DEV_IMGTEC_HASH is not set
+# CONFIG_CRYPTO_DEV_SAFEXCEL is not set
+# CONFIG_CRYPTO_DEV_CCREE is not set
+CONFIG_ASYMMETRIC_KEY_TYPE=y
+CONFIG_ASYMMETRIC_PUBLIC_KEY_SUBTYPE=y
+CONFIG_X509_CERTIFICATE_PARSER=y
+# CONFIG_PKCS8_PRIVATE_KEY_PARSER is not set
+CONFIG_PKCS7_MESSAGE_PARSER=y
+# CONFIG_PKCS7_TEST_KEY is not set
+# CONFIG_SIGNED_PE_FILE_VERIFICATION is not set
+
+#
+# Certificates for signature checking
+#
+CONFIG_SYSTEM_TRUSTED_KEYRING=y
+CONFIG_SYSTEM_TRUSTED_KEYS=""
+# CONFIG_SYSTEM_EXTRA_CERTIFICATE is not set
+# CONFIG_SECONDARY_TRUSTED_KEYRING is not set
+# CONFIG_SYSTEM_BLACKLIST_KEYRING is not set
+# end of Certificates for signature checking
+
+#
+# Library routines
+#
+# CONFIG_PACKING is not set
+CONFIG_BITREVERSE=y
+CONFIG_GENERIC_NET_UTILS=y
+# CONFIG_CORDIC is not set
+CONFIG_NO_GENERIC_PCI_IOPORT_MAP=y
+CONFIG_GENERIC_PCI_IOMAP=y
+CONFIG_GENERIC_IOMAP=y
+CONFIG_CRC_CCITT=y
+# CONFIG_CRC16 is not set
+# CONFIG_CRC_T10DIF is not set
+# CONFIG_CRC_ITU_T is not set
+CONFIG_CRC32=y
+# CONFIG_CRC32_SELFTEST is not set
+CONFIG_CRC32_SLICEBY8=y
+# CONFIG_CRC32_SLICEBY4 is not set
+# CONFIG_CRC32_SARWATE is not set
+# CONFIG_CRC32_BIT is not set
+# CONFIG_CRC64 is not set
+# CONFIG_CRC4 is not set
+# CONFIG_CRC7 is not set
+# CONFIG_LIBCRC32C is not set
+# CONFIG_CRC8 is not set
+# CONFIG_RANDOM32_SELFTEST is not set
+CONFIG_XZ_DEC=y
+# CONFIG_XZ_DEC_X86 is not set
+# CONFIG_XZ_DEC_POWERPC is not set
+# CONFIG_XZ_DEC_IA64 is not set
+# CONFIG_XZ_DEC_ARM is not set
+# CONFIG_XZ_DEC_ARMTHUMB is not set
+# CONFIG_XZ_DEC_SPARC is not set
+# CONFIG_XZ_DEC_TEST is not set
+CONFIG_DECOMPRESS_LZMA=y
+CONFIG_TEXTSEARCH=y
+# CONFIG_TEXTSEARCH_KMP is not set
+# CONFIG_TEXTSEARCH_BM is not set
+# CONFIG_TEXTSEARCH_FSM is not set
+CONFIG_ASSOCIATIVE_ARRAY=y
+CONFIG_HAS_IOMEM=y
+CONFIG_HAS_IOPORT_MAP=y
+CONFIG_HAS_DMA=y
+CONFIG_NEED_DMA_MAP_STATE=y
+CONFIG_ARCH_HAS_DMA_WRITE_COMBINE=y
+CONFIG_DMA_DECLARE_COHERENT=y
+CONFIG_ARCH_HAS_SYNC_DMA_FOR_DEVICE=y
+CONFIG_ARCH_HAS_DMA_PREP_COHERENT=y
+CONFIG_ARCH_HAS_DMA_COHERENT_TO_PFN=y
+CONFIG_DMA_NONCOHERENT_CACHE_SYNC=y
+CONFIG_DMA_API_DEBUG=y
+CONFIG_DMA_API_DEBUG_SG=y
+CONFIG_DQL=y
+CONFIG_NLATTR=y
+CONFIG_GENERIC_ATOMIC64=y
+CONFIG_CLZ_TAB=y
+# CONFIG_IRQ_POLL is not set
+CONFIG_MPILIB=y
+CONFIG_LIBFDT=y
+CONFIG_OID_REGISTRY=y
+CONFIG_HAVE_GENERIC_VDSO=y
+CONFIG_GENERIC_GETTIMEOFDAY=y
+# CONFIG_STRING_SELFTEST is not set
+# end of Library routines
+
+CONFIG_GENERIC_LIB_ASHLDI3=y
+CONFIG_GENERIC_LIB_ASHRDI3=y
+CONFIG_GENERIC_LIB_LSHRDI3=y
+CONFIG_GENERIC_LIB_CMPDI2=y
+CONFIG_GENERIC_LIB_UCMPDI2=y
+
+#
+# Kernel hacking
+#
+
+#
+# printk and dmesg options
+#
+CONFIG_PRINTK_TIME=y
+# CONFIG_PRINTK_CALLER is not set
+CONFIG_CONSOLE_LOGLEVEL_DEFAULT=7
+CONFIG_CONSOLE_LOGLEVEL_QUIET=4
+CONFIG_MESSAGE_LOGLEVEL_DEFAULT=4
+# CONFIG_BOOT_PRINTK_DELAY is not set
+# CONFIG_DYNAMIC_DEBUG is not set
+# end of printk and dmesg options
+
+#
+# Compile-time checks and compiler options
+#
+CONFIG_DEBUG_INFO=y
+CONFIG_DEBUG_INFO_REDUCED=y
+# CONFIG_DEBUG_INFO_SPLIT is not set
+# CONFIG_DEBUG_INFO_DWARF4 is not set
+# CONFIG_GDB_SCRIPTS is not set
+CONFIG_ENABLE_MUST_CHECK=y
+CONFIG_FRAME_WARN=1024
+# CONFIG_STRIP_ASM_SYMS is not set
+# CONFIG_READABLE_ASM is not set
+CONFIG_DEBUG_FS=y
+# CONFIG_HEADERS_INSTALL is not set
+CONFIG_OPTIMIZE_INLINING=y
+# CONFIG_DEBUG_SECTION_MISMATCH is not set
+CONFIG_SECTION_MISMATCH_WARN_ONLY=y
+# CONFIG_DEBUG_FORCE_WEAK_PER_CPU is not set
+# end of Compile-time checks and compiler options
+
+CONFIG_MAGIC_SYSRQ=y
+CONFIG_MAGIC_SYSRQ_DEFAULT_ENABLE=0x1
+# CONFIG_MAGIC_SYSRQ_SERIAL is not set
+CONFIG_DEBUG_KERNEL=y
+# CONFIG_DEBUG_MISC is not set
+
+#
+# Memory Debugging
+#
+# CONFIG_PAGE_EXTENSION is not set
+# CONFIG_DEBUG_PAGEALLOC is not set
+# CONFIG_PAGE_OWNER is not set
+# CONFIG_PAGE_POISONING is not set
+# CONFIG_DEBUG_OBJECTS is not set
+# CONFIG_DEBUG_SLAB is not set
+CONFIG_HAVE_DEBUG_KMEMLEAK=y
+# CONFIG_DEBUG_KMEMLEAK is not set
+# CONFIG_DEBUG_STACK_USAGE is not set
+# CONFIG_DEBUG_VM is not set
+# CONFIG_DEBUG_MEMORY_INIT is not set
+CONFIG_HAVE_DEBUG_STACKOVERFLOW=y
+# CONFIG_DEBUG_STACKOVERFLOW is not set
+CONFIG_CC_HAS_KASAN_GENERIC=y
+CONFIG_KASAN_STACK=1
+# end of Memory Debugging
+
+CONFIG_CC_HAS_SANCOV_TRACE_PC=y
+# CONFIG_DEBUG_SHIRQ is not set
+
+#
+# Debug Lockups and Hangs
+#
+# CONFIG_SOFTLOCKUP_DETECTOR is not set
+# CONFIG_DETECT_HUNG_TASK is not set
+# CONFIG_WQ_WATCHDOG is not set
+# end of Debug Lockups and Hangs
+
+# CONFIG_PANIC_ON_OOPS is not set
+CONFIG_PANIC_ON_OOPS_VALUE=0
+CONFIG_PANIC_TIMEOUT=0
+CONFIG_SCHED_DEBUG=y
+# CONFIG_SCHEDSTATS is not set
+# CONFIG_SCHED_STACK_END_CHECK is not set
+# CONFIG_DEBUG_TIMEKEEPING is not set
+
+#
+# Lock Debugging (spinlocks, mutexes, etc...)
+#
+CONFIG_LOCK_DEBUGGING_SUPPORT=y
+# CONFIG_PROVE_LOCKING is not set
+# CONFIG_LOCK_STAT is not set
+# CONFIG_DEBUG_RT_MUTEXES is not set
+# CONFIG_DEBUG_SPINLOCK is not set
+# CONFIG_DEBUG_MUTEXES is not set
+# CONFIG_DEBUG_WW_MUTEX_SLOWPATH is not set
+# CONFIG_DEBUG_RWSEMS is not set
+# CONFIG_DEBUG_LOCK_ALLOC is not set
+# CONFIG_DEBUG_ATOMIC_SLEEP is not set
+# CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set
+# CONFIG_LOCK_TORTURE_TEST is not set
+# CONFIG_WW_MUTEX_SELFTEST is not set
+# end of Lock Debugging (spinlocks, mutexes, etc...)
+
+CONFIG_STACKTRACE=y
+# CONFIG_WARN_ALL_UNSEEDED_RANDOM is not set
+# CONFIG_DEBUG_KOBJECT is not set
+# CONFIG_DEBUG_LIST is not set
+# CONFIG_DEBUG_PLIST is not set
+# CONFIG_DEBUG_SG is not set
+# CONFIG_DEBUG_NOTIFIERS is not set
+# CONFIG_DEBUG_CREDENTIALS is not set
+
+#
+# RCU Debugging
+#
+# CONFIG_RCU_PERF_TEST is not set
+# CONFIG_RCU_TORTURE_TEST is not set
+# CONFIG_RCU_TRACE is not set
+# CONFIG_RCU_EQS_DEBUG is not set
+# end of RCU Debugging
+
+# CONFIG_DEBUG_WQ_FORCE_RR_CPU is not set
+# CONFIG_NOTIFIER_ERROR_INJECTION is not set
+# CONFIG_FAULT_INJECTION is not set
+# CONFIG_LATENCYTOP is not set
+CONFIG_HAVE_FUNCTION_TRACER=y
+CONFIG_HAVE_FUNCTION_GRAPH_TRACER=y
+CONFIG_HAVE_DYNAMIC_FTRACE=y
+CONFIG_HAVE_FTRACE_MCOUNT_RECORD=y
+CONFIG_HAVE_SYSCALL_TRACEPOINTS=y
+CONFIG_HAVE_C_RECORDMCOUNT=y
+CONFIG_TRACING_SUPPORT=y
+# CONFIG_FTRACE is not set
+# CONFIG_RUNTIME_TESTING_MENU is not set
+# CONFIG_MEMTEST is not set
+# CONFIG_BUG_ON_DATA_CORRUPTION is not set
+# CONFIG_SAMPLES is not set
+CONFIG_HAVE_ARCH_KGDB=y
+# CONFIG_KGDB is not set
+CONFIG_ARCH_HAS_UBSAN_SANITIZE_ALL=y
+# CONFIG_UBSAN is not set
+CONFIG_UBSAN_ALIGNMENT=y
+CONFIG_TRACE_IRQFLAGS_SUPPORT=y
+CONFIG_EARLY_PRINTK=y
+CONFIG_CMDLINE_BOOL=y
+CONFIG_CMDLINE="console=ttyS0,57600"
+# CONFIG_CMDLINE_OVERRIDE is not set
+# CONFIG_DEBUG_ZBOOT is not set
+# CONFIG_SPINLOCK_TEST is not set
+# CONFIG_SCACHE_DEBUGFS is not set
+# end of Kernel hacking
+CONFIG_NEW_LEDS=y
+CONFIG_LEDS_CLASS=y
+CONFIG_GPIO_RALINK=y
+CONFIG_GPIOLIB=y
+CONFIG_GPIOLIB_FASTPATH_LIMIT=512
+CONFIG_OF_GPIO=y
+CONFIG_GPIO_SYSFS=y
diff --git a/target/linux/ramips/rt6855a/profiles/00-default.mk b/target/linux/ramips/rt6855a/profiles/00-default.mk
new file mode 100644
index 0000000000..c0706254c7
--- /dev/null
+++ b/target/linux/ramips/rt6855a/profiles/00-default.mk
@@ -0,0 +1,17 @@
+#
+# Copyright (C) 2011 OpenWrt.org
+#
+# This is free software, licensed under the GNU General Public License v2.
+# See /LICENSE for more information.
+#
+
+define Profile/Default
+ NAME:=Default Profile
+ PRIORITY:=1
+ PACKAGES:=
+endef
+
+define Profile/Default/Description
+ Default package set compatible with most boards.
+endef
+$(eval $(call Profile,Default))
diff --git a/target/linux/ramips/rt6855a/target.mk b/target/linux/ramips/rt6855a/target.mk
new file mode 100644
index 0000000000..0efedf4fde
--- /dev/null
+++ b/target/linux/ramips/rt6855a/target.mk
@@ -0,0 +1,15 @@
+#
+# Copyright (C) 2009 OpenWrt.org
+#
+
+SUBTARGET:=rt6855a
+BOARDNAME:=RT6855A based boards
+FEATURES+=ramdisk pci
+CPU_TYPE:=34kc
+
+DEFAULT_PACKAGES += wpad-basic-wolfssl swconfig
+
+define Target/Description
+ Build firmware images for Ralink RT6855A based boards.
+endef
+
--
2.27.0
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