[OpenWrt-Devel] [PATCH v2 0/7] MIPS: lantiq: irq: Various fixes, add SMP support

[Paul Burton]

Hello,

petrcvekcz at gmail.com wrote:
> From: Petr Cvek <petrcvekcz at gmail.com>
> 
> Hi,
> 
> While hacking with my modem in openwrt I've found in the lantiq vrx268 SoC
> there is only a support for the processes SMP and not for interrupt
> routing. After some looking into vendors released source codes (probably
> intel UGW) and by observing SoC's memory map I've found out there is
> a second interrupt controller (ICU) for the second VPE. The last patch of
> this series adds a support for it. The code is different from intel UGW's
> set affinity function, where the interrupt line gets enabled (switched)
> to the second ICU. Instead only the cpumask gets changed in my set affinity.
> The change will be written into the hardware after the next irq enable call.
> This was changed because of stability reasons in the high irq load of
> the SoC.
> 
> The first part of the series are more or less cosmetic changes of long
> names, different types and few fixed warnings from checkpatch. There is
> a fix in part 5, where I've found the missing bitfield clear before ORing
> with a new value.
> 
> The SMP in part 7 changes devicetree definition for a register regions
> of the ICU. Previously, there was a region for a single IM (a mask/unmask/
> enable/... set for 32 interrupts). Now it is the whole ICU. It match more
> the hardware layout. There is no compatibility issue in vanilla, only
> openwrt was affected by these devicetrees.
> 
> Also in the UGW's ltq_enable_irq(), there was a status bit reset before
> the actual IRQ line enable. It was marked as "Bug fix for fake interrupt".
> The code seems to work without it (vanilla and new SMP), but I've made
> an assert if this bit is set before the actual enable. The assert reported
> these IRQ sources:
> 
> 22:00004000     spi_rx  (only when SPI is accessed)
> 63:00800000     mei_cpe (permanent 1s)
> 112:00000100    asc_tx
> 
> But the code seems to run anyway I didn't include the status bit reset part.
> 
> The SMP affinity update is done every IRQ enable, where it extract the first
> valid VPE from affinity cpumask. This is standard in the kernel.
> 
> The code was tested in nosmp configuration on TPLink W9980B in openwrt tree
> (patched kernel v4.14). The lantiq devices other than vrx268 were not
> tested.
> 
> Discussion on openwrt related parts for lantiq ICU SMP is here (devicetrees,
> things not in the vanilla kernel, RFC versions of the patch):
> https://patchwork.ozlabs.org/patch/1100832/
> 
> Changes since v1:
> * Added a define for IM size
> * Changed ltq_icu_membase array size to NR_CPUS so for_each_possible_cpu()
> will not overflow
> * Removed affinity auto rotation (can be add later from v1 if required)
> * Commit messages wordings
> 
> Petr Cvek (7):
> MIPS: lantiq: Move macro directly to iomem function
> MIPS: lantiq: Change variables to the same type as the source
> MIPS: lantiq: Fix attributes of of_device_id structure
> MIPS: lantiq: Remove unused macros
> MIPS: lantiq: Fix bitfield masking
> MIPS: lantiq: Shorten register names, remove unused macros
> MIPS: lantiq: Add SMP support for lantiq interrupt controller
> 
> arch/mips/lantiq/irq.c | 177 +++++++++++++++++++++++++++++------------
> 1 file changed, 126 insertions(+), 51 deletions(-)

Series applied to mips-next.

Thanks,
    Paul

[ This message was auto-generated; if you believe anything is incorrect
  then please email paul.burton at mips.com to report it. ]
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