[OpenWrt-Devel] [PATCH] kernel: MIPS: math-emu Write-protect delay slot emulation pages

[Rosen Penev]

On Sun, Dec 23, 2018 at 2:27 AM Kevin 'ldir' Darbyshire-Bryant
<ldir at darbyshire-bryant.me.uk> wrote:
>
>
>
> > On 23 Dec 2018, at 09:43, Kevin 'ldir' Darbyshire-Bryant <ldir at darbyshire-bryant.me.uk> wrote:
> >
> > I’d suggest putting the champagne away for the moment.  I’m not convinced and I’ll explain why after a bit more checking.
>
> TL;DR - I don’t think the mips processor, certainly in the Archer c7 supports ri/xi.
I tried out Hauke's patch on mt7621. Both rixiex and rixi show up.
>
> I dropped the cpu_has_rixi 0 override in 0014-MIPS-ath79-finetune-cpu-overrides.patch.  I then patched the kernel to dump a little bit more info from /proc/cpuinfo:
>
> diff --git a/arch/mips/kernel/proc.c b/arch/mips/kernel/proc.c
> index b2de408a2..3ae85c792 100644
> --- a/arch/mips/kernel/proc.c
> +++ b/arch/mips/kernel/proc.c
> @@ -126,6 +126,9 @@ static int show_cpuinfo(struct seq_file *m, void *v)
>         if (cpu_has_xpa)        seq_printf(m, "%s", " xpa");
>         seq_printf(m, "\n");
>
> +       seq_printf(m, "rixi used:\t: %s\n", cpu_has_rixi ?  "yes" : "no");
> +       seq_printf(m, "config3:\t: %X %X\n", (read_c0_config3() >> 16), read_c0_config3());
> +
>         if (cpu_has_mmips) {
>                 seq_printf(m, "micromips kernel\t: %s\n",
>                       (read_c0_config3() & MIPS_CONF3_ISA_OE) ?  "yes" : "no");
>
>
> cat /proc/cpuinfo
> system type             : Qualcomm Atheros QCA9558 ver 1 rev 0
> machine                 : TP-Link Archer C7 Version 2
> processor               : 0
> cpu model               : MIPS 74Kc V5.0
> BogoMIPS                : 358.80
> wait instruction        : yes
> microsecond timers      : yes
> tlb_entries             : 32
> extra interrupt vector  : yes
> hardware watchpoint     : yes, count: 4, address/irw mask: [0x0ffc, 0x0ffc, 0x0ffb, 0x0ffb]
> isa                     : mips1 mips2 mips32r1 mips32r2
> ASEs implemented        : mips16 dsp dsp2
> rixi used:      : no
> config3:        : 0 2E28
> shadow register sets    : 1
> kscratch registers      : 0
> package                 : 0
> core                    : 0
> VCED exceptions         : not available
> VCEI exceptions         : not available
>
> According to the doc Hauke linked on page 235 here: https://s3-eu-west-1.amazonaws.com/downloads-mips/I7200/I7200+product+launch/MIPS_nanoMIPS32_PRA_06_09_MD01251.pdf bit 12 of config3 is the flag of interest.  0x2E28 does not set bit 12, so "The RIE and XIE bits are not implemented within the PageGrain register."
>
> There is a remaining mystery related to the config3 register.  The documentation claims it to be 32 bits wide yet none of the top 16 bits are set (and I even shifted them down in case the printf couldn’t cope) so I remain confused.
>
> In terms of the ath79-finetune-cpu-overrides.patch, why do it? Optimisation.  The cpu_has_foo options are macros which if forced to 0/1 enable the compile to exclude/include code at build time…so like many things Openwrt it’s a size thing…. well as far as I understand it.
>
> I’m now concentrating on the festive period in the comfort that at least I’ve had a go at backporting the fpu writeable page fix with I think success (yet to be committed) and I have a little more grasp of what rixi means.
>
> Kevin
>
>

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