[OpenWrt-Devel] [PATCH] [RESEND] [ar71xx] enable PLC support on DHP-1565 board

[John Crispin]

Hi,

patch is still heavily broken. please try sending it to yourself until
you can apply it with "git am" once that works feel free to resend. also
try to use git to send the patch, this will make it alot easier for yourself

	John


On 16/02/2016 10:58, Basse, Frederic wrote:
> Enable port 6 of AR8327 switch on DHP-1565 board to allow communication
> between CPU & AR7400 PLC chipset.
> 
> Signed-off-by: Frédéric Basse <contact at fredericb.info>
> ---
>  target/linux/ar71xx/files/arch/mips/ath79/mach-dhp-1565-a1.c | 16
> ++++++++++++++++
>  1 file changed, 16 insertions(+)
> 
> diff --git
> a/target/linux/ar71xx/files/arch/mips/ath79/mach-dhp-1565-a1.c
> b/target/linux/ar71xx/files/arch/mips/ath79/mach-dhp-1565-a1.c
> index ae47764..2963463 100644
> --- a/target/linux/ar71xx/files/arch/mips/ath79/mach-dhp-1565-a1.c
> +++ b/target/linux/ar71xx/files/arch/mips/ath79/mach-dhp-1565-a1.c
> @@ -100,8 +100,17 @@ static struct ar8327_pad_cfg
> dhp1565a1_ar8327_pad0_cfg = {
>  	.rxclk_delay_sel = AR8327_CLK_DELAY_SEL2,
>  };
> 
> +static struct ar8327_pad_cfg dhp1565a1_ar8327_pad6_cfg = {
> +	.mode = AR8327_PAD_MAC_RGMII,
> +	.txclk_delay_en = false,
> +	.rxclk_delay_en = true,
> +	.txclk_delay_sel = AR8327_CLK_DELAY_SEL0,
> +	.rxclk_delay_sel = AR8327_CLK_DELAY_SEL0,
> +};
> +
>  static struct ar8327_platform_data dhp1565a1_ar8327_data = {
>  	.pad0_cfg = &dhp1565a1_ar8327_pad0_cfg,
> +	.pad6_cfg = &dhp1565a1_ar8327_pad6_cfg,
>  	.port0_cfg = {
>  		.force_link = 1,
>  		.speed = AR8327_PORT_SPEED_1000,
> @@ -109,6 +118,13 @@ static struct ar8327_platform_data
> dhp1565a1_ar8327_data = {
>  		.txpause = 1,
>  		.rxpause = 1,
>  	},
> +	.port6_cfg = {
> +		.force_link = 1,
> +		.speed = AR8327_PORT_SPEED_1000,
> +		.duplex = 1,
> +		.txpause = 1,
> +		.rxpause = 1,
> +	},
>  };
> 
>  static struct mdio_board_info dhp1565a1_mdio0_info[] = {
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