[OpenWrt-Devel] uboot-lantiq cgu settings for ramboot image

[Ben Mulvihill]

Hi Daniel,

On Mon, 2015-01-19 at 14:57 +0100, Daniel Schwierzeck wrote:
> Hi Ben,
> 
> 2015-01-19 11:46 GMT+01:00 Ben Mulvihill <ben.mulvihill at gmail.com>:
> > Hello,
> >
> > I am trying to build uboot-lantiq for the BT Home Hub 3A (lantiq
> > ar9), and am wondering where to initialise the cgu, in the case
> > of a ramboot image for uart booting. Normally the cgu is initialised
> > in lowlevel_init, but that code is bypassed in ramboot images. The
> > result is that the board boots with the wrong cgu settings, which
> > sends the console haywire. So far I have tried two solutions:
> >
> > - putting the following lines in board_early_init_f:
> >
> >   #define REG32(addr) *((volatile u32 *)(addr))
> >         REG32(0xbf103010) = 0x80;
> >         REG32(0xbf103014) = 0x01;
> >
> >   This fixes the console, but breaks ethernet. I am wondering
> >   whether this is because by putting this code in this place, I
> >   am altering the cgu settings after setting up ram. Is this
> >   admissible?
> 
> it is insufficient if you want to change the DDR clock after the
> memory is already initialized. For that you will need a sequence like
> putting memory in self-refresh mode, stopping memory controller,
> update clocks, restart memory controller, putting memory out of
> self-refresh. That's why the cgu_init() runs before mc_init(). Thus if
> the board comes up with 111/111 MHz, you cannot switch to 393/166 MHz
> because that would require to change the DDR clock.
> 
Thank you for the explanations. I suspected that something like that
was the problem. I'll have a do at doing the full sequence you describe.

> >
> > - adding the same two register settings to the start of the
> >   ddr_settings file generated by lantiq_ram_init_uart.awk .
> >   However, the resulting image gives a download error and won't
> >   boot at all.
> 
> Actually this should work. Did you put the CGU register settings
> before the memory controller settings?
> 
I did. The start of my ddr_settings file looked like this:
    0xbf103010 0x80
    0xbf103014 0x01
    0xbf800010 0x0
    0xbf800020 0x0
    0xbf800060 0xD
    0xbf801030 0x0
    0xbf801000 0x1b1b

> >
> > Any suggestions will be gratefully received!
> >
> > Ben
> >
> >
> 
Ben
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