[OpenWrt-Devel] ramips: MT7621 all ethernet interrupts to CPU0?

[John Crispin]

On 18/12/2015 15:19, Cristian Morales Vega wrote:
> I am far from an expert here. Somebody knows if this is to be expected?

with the kernel now running the GIC we actually should have a fully
functional irq affinity setup. might make sense to put the pic irqs on a
secondary core

> 
> root at OpenWrt:/tmp# cat /proc/irq/11/smp_affinity_list
> 0-3
> root at OpenWrt:/tmp# cat /proc/interrupts
>            CPU0       CPU1       CPU2       CPU3
>   7:     211536     211092     211160     212477      MIPS   7  timer
>  11:     122753          0          0          0  MIPS GIC   3
> 1e100000.ethernet
>  30:         80          0          0          0  MIPS GIC  22  xhci-hcd:usb1
>  31:         12          0          0          0  MIPS GIC  23  gsw
>  34:      18902          0          0          0  MIPS GIC  26  serial
>  64:     373599          0          0          0  MIPS GIC  56  ipi resched
>  65:          0     126946          0          0  MIPS GIC  57  ipi resched
>  66:          0          0     156843          0  MIPS GIC  58  ipi resched
>  67:          0          0          0      99421  MIPS GIC  59  ipi resched
>  68:       1269          0          0          0  MIPS GIC  60  ipi call
>  69:          0       5279          0          0  MIPS GIC  61  ipi call
>  70:          0          0       4708          0  MIPS GIC  62  ipi call
>  71:          0          0          0      51383  MIPS GIC  63  ipi call
> ERR:          1
> 
> I am using Chaos Calmer.
> _______________________________________________
> openwrt-devel mailing list
> openwrt-devel at lists.openwrt.org
> https://lists.openwrt.org/cgi-bin/mailman/listinfo/openwrt-devel
> 
_______________________________________________
openwrt-devel mailing list
openwrt-devel at lists.openwrt.org
https://lists.openwrt.org/cgi-bin/mailman/listinfo/openwrt-devel