[OpenWrt-Devel] [PATCH 4/6] ramips: change CM_GCR_BASE_CMDEFTGT_MEM value to match datasheet

[Nikolay Martynov]

Zero config value for default memory region means 'memory', not
not 'disabled' according to 'Control Registers Of The Coherency
Manager' manual.

Signed-off-by: Nikolay Martynov <mar.kolya at gmail.com>
---
 ...set-CM_GCR_BASE_CMDEFTGT_MEM-according-to-datasheet.patch | 12 ++++++++++++
 1 file changed, 12 insertions(+)
 create mode 100644 target/linux/ramips/patches-4.3/0063-set-CM_GCR_BASE_CMDEFTGT_MEM-according-to-datasheet.patch

diff --git a/target/linux/ramips/patches-4.3/0063-set-CM_GCR_BASE_CMDEFTGT_MEM-according-to-datasheet.patch b/target/linux/ramips/patches-4.3/0063-set-CM_GCR_BASE_CMDEFTGT_MEM-according-to-datasheet.patch
new file mode 100644
index 0000000..6b9e9e3
--- /dev/null
+++ b/target/linux/ramips/patches-4.3/0063-set-CM_GCR_BASE_CMDEFTGT_MEM-according-to-datasheet.patch
@@ -0,0 +1,12 @@
+--- a/arch/mips/include/asm/mips-cm.h
++++ b/arch/mips/include/asm/mips-cm.h
+@@ -225,8 +225,7 @@ BUILD_CM_Cx_R_(tcid_8_priority,	0x80)
+ #define CM_GCR_BASE_GCRBASE_MSK			(_ULCAST_(0x1ffff) << 15)
+ #define CM_GCR_BASE_CMDEFTGT_SHF		0
+ #define CM_GCR_BASE_CMDEFTGT_MSK		(_ULCAST_(0x3) << 0)
+-#define  CM_GCR_BASE_CMDEFTGT_DISABLED		0
+-#define  CM_GCR_BASE_CMDEFTGT_MEM		1
++#define  CM_GCR_BASE_CMDEFTGT_MEM		0
+ #define  CM_GCR_BASE_CMDEFTGT_IOCU0		2
+ #define  CM_GCR_BASE_CMDEFTGT_IOCU1		3
+ 
-- 
2.6.4
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