[OpenWrt-Devel] [PATCH] imx6: backport some upstream ventana patches

Tim Harvey tharvey at gateworks.com
Wed Dec 2 11:11:14 EST 2015 

This backports some patches that have been accepted to the upstream kernel
for ventana

Signed-off-by: Tim Harvey <tharvey at gateworks.com>
---
 ...tana-add-UHS-I-support-for-Ventana-boards.patch | 212 +++++++++++++++++
 .../040-ARM-dts-imx-ventana-add-pwm-nodes.patch    | 264 +++++++++++++++++++++
 ...ts-imx-ventana-add-spi-support-for-gw52xx.patch |  33 +++
 3 files changed, 509 insertions(+)
 create mode 100644 target/linux/imx6/patches-4.1/030-ARM-dts-ventana-add-UHS-I-support-for-Ventana-boards.patch
 create mode 100644 target/linux/imx6/patches-4.1/040-ARM-dts-imx-ventana-add-pwm-nodes.patch
 create mode 100644 target/linux/imx6/patches-4.1/041-ARM-dts-imx-ventana-add-spi-support-for-gw52xx.patch

diff --git a/target/linux/imx6/patches-4.1/030-ARM-dts-ventana-add-UHS-I-support-for-Ventana-boards.patch b/target/linux/imx6/patches-4.1/030-ARM-dts-ventana-add-UHS-I-support-for-Ventana-boards.patch
new file mode 100644
index 0000000..0165236
--- /dev/null
+++ b/target/linux/imx6/patches-4.1/030-ARM-dts-ventana-add-UHS-I-support-for-Ventana-boards.patch
@@ -0,0 +1,212 @@
+--- a/arch/arm/boot/dts/imx6qdl-gw51xx.dtsi
++++ b/arch/arm/boot/dts/imx6qdl-gw51xx.dtsi
+@@ -323,7 +323,6 @@
+ 				MX6QDL_PAD_NANDF_WP_B__NAND_WP_B	0xb0b1
+ 				MX6QDL_PAD_NANDF_RB0__NAND_READY_B	0xb000
+ 				MX6QDL_PAD_NANDF_CS0__NAND_CE0_B	0xb0b1
+-				MX6QDL_PAD_NANDF_CS1__NAND_CE1_B	0xb0b1
+ 				MX6QDL_PAD_SD4_CMD__NAND_RE_B		0xb0b1
+ 				MX6QDL_PAD_SD4_CLK__NAND_WE_B		0xb0b1
+ 				MX6QDL_PAD_NANDF_D0__NAND_DATA00	0xb0b1
+--- a/arch/arm/boot/dts/imx6qdl-gw52xx.dtsi
++++ b/arch/arm/boot/dts/imx6qdl-gw52xx.dtsi
+@@ -386,10 +386,13 @@
+ };
+ 
+ &usdhc3 {
+-	pinctrl-names = "default";
++	pinctrl-names = "default", "state_100mhz", "state_200mhz";
+ 	pinctrl-0 = <&pinctrl_usdhc3>;
++	pinctrl-1 = <&pinctrl_usdhc3_100mhz>;
++	pinctrl-2 = <&pinctrl_usdhc3_200mhz>;
+ 	cd-gpios = <&gpio7 0 GPIO_ACTIVE_HIGH>;
+ 	vmmc-supply = <&reg_3p3v>;
++	no-1-8-v; /* firmware will remove if board revision supports */
+ 	status = "okay";
+ };
+ 
+@@ -450,7 +453,6 @@
+ 				MX6QDL_PAD_NANDF_WP_B__NAND_WP_B	0xb0b1
+ 				MX6QDL_PAD_NANDF_RB0__NAND_READY_B	0xb000
+ 				MX6QDL_PAD_NANDF_CS0__NAND_CE0_B	0xb0b1
+-				MX6QDL_PAD_NANDF_CS1__NAND_CE1_B	0xb0b1
+ 				MX6QDL_PAD_SD4_CMD__NAND_RE_B		0xb0b1
+ 				MX6QDL_PAD_SD4_CLK__NAND_WE_B		0xb0b1
+ 				MX6QDL_PAD_NANDF_D0__NAND_DATA00	0xb0b1
+@@ -552,7 +554,34 @@
+ 				MX6QDL_PAD_SD3_DAT1__SD3_DATA1		0x17059
+ 				MX6QDL_PAD_SD3_DAT2__SD3_DATA2		0x17059
+ 				MX6QDL_PAD_SD3_DAT3__SD3_DATA3		0x17059
+-				MX6QDL_PAD_SD3_DAT5__GPIO7_IO00	0x1b0b0 /* CD */
++				MX6QDL_PAD_SD3_DAT5__GPIO7_IO00		0x17059 /* CD */
++				MX6QDL_PAD_NANDF_CS1__SD3_VSELECT	0x17059
++			>;
++		};
++
++		pinctrl_usdhc3_100mhz: usdhc3grp100mhz {
++			fsl,pins = <
++				MX6QDL_PAD_SD3_CMD__SD3_CMD		0x170b9
++				MX6QDL_PAD_SD3_CLK__SD3_CLK		0x170b9
++				MX6QDL_PAD_SD3_DAT0__SD3_DATA0		0x170b9
++				MX6QDL_PAD_SD3_DAT1__SD3_DATA1		0x170b9
++				MX6QDL_PAD_SD3_DAT2__SD3_DATA2		0x170b9
++				MX6QDL_PAD_SD3_DAT3__SD3_DATA3		0x170b9
++				MX6QDL_PAD_SD3_DAT5__GPIO7_IO00		0x170b9 /* CD */
++				MX6QDL_PAD_NANDF_CS1__SD3_VSELECT	0x170b9
++			>;
++		};
++
++		pinctrl_usdhc3_200mhz: usdhc3grp200mhz {
++			fsl,pins = <
++				MX6QDL_PAD_SD3_CMD__SD3_CMD		0x170f9
++				MX6QDL_PAD_SD3_CLK__SD3_CLK		0x100f9
++				MX6QDL_PAD_SD3_DAT0__SD3_DATA0		0x170f9
++				MX6QDL_PAD_SD3_DAT1__SD3_DATA1		0x170f9
++				MX6QDL_PAD_SD3_DAT2__SD3_DATA2		0x170f9
++				MX6QDL_PAD_SD3_DAT3__SD3_DATA3		0x170f9
++				MX6QDL_PAD_SD3_DAT5__GPIO7_IO00		0x170f9 /* CD */
++				MX6QDL_PAD_NANDF_CS1__SD3_VSELECT	0x170f9
+ 			>;
+ 		};
+ 	};
+--- a/arch/arm/boot/dts/imx6qdl-gw53xx.dtsi
++++ b/arch/arm/boot/dts/imx6qdl-gw53xx.dtsi
+@@ -393,10 +393,13 @@
+ };
+ 
+ &usdhc3 {
+-	pinctrl-names = "default";
++	pinctrl-names = "default", "state_100mhz", "state_200mhz";
+ 	pinctrl-0 = <&pinctrl_usdhc3>;
++	pinctrl-1 = <&pinctrl_usdhc3_100mhz>;
++	pinctrl-2 = <&pinctrl_usdhc3_200mhz>;
+ 	cd-gpios = <&gpio7 0 GPIO_ACTIVE_HIGH>;
+ 	vmmc-supply = <&reg_3p3v>;
++	no-1-8-v; /* firmware will remove if board revision supports */
+ 	status = "okay";
+ };
+ 
+@@ -456,7 +459,6 @@
+ 				MX6QDL_PAD_NANDF_WP_B__NAND_WP_B	0xb0b1
+ 				MX6QDL_PAD_NANDF_RB0__NAND_READY_B	0xb000
+ 				MX6QDL_PAD_NANDF_CS0__NAND_CE0_B	0xb0b1
+-				MX6QDL_PAD_NANDF_CS1__NAND_CE1_B	0xb0b1
+ 				MX6QDL_PAD_SD4_CMD__NAND_RE_B		0xb0b1
+ 				MX6QDL_PAD_SD4_CLK__NAND_WE_B		0xb0b1
+ 				MX6QDL_PAD_NANDF_D0__NAND_DATA00	0xb0b1
+@@ -560,7 +562,34 @@
+ 				MX6QDL_PAD_SD3_DAT1__SD3_DATA1		0x17059
+ 				MX6QDL_PAD_SD3_DAT2__SD3_DATA2		0x17059
+ 				MX6QDL_PAD_SD3_DAT3__SD3_DATA3		0x17059
+-				MX6QDL_PAD_SD3_DAT5__GPIO7_IO00		0x1b0b0 /* CD */
++				MX6QDL_PAD_SD3_DAT5__GPIO7_IO00		0x17059 /* CD */
++				MX6QDL_PAD_NANDF_CS1__SD3_VSELECT	0x17059
++			>;
++		};
++
++		pinctrl_usdhc3_100mhz: usdhc3grp100mhz {
++			fsl,pins = <
++				MX6QDL_PAD_SD3_CMD__SD3_CMD		0x170b9
++				MX6QDL_PAD_SD3_CLK__SD3_CLK		0x100b9
++				MX6QDL_PAD_SD3_DAT0__SD3_DATA0		0x170b9
++				MX6QDL_PAD_SD3_DAT1__SD3_DATA1		0x170b9
++				MX6QDL_PAD_SD3_DAT2__SD3_DATA2		0x170b9
++				MX6QDL_PAD_SD3_DAT3__SD3_DATA3		0x170b9
++				MX6QDL_PAD_SD3_DAT5__GPIO7_IO00		0x170b9 /* CD */
++				MX6QDL_PAD_NANDF_CS1__SD3_VSELECT	0x170b9
++			>;
++		};
++
++		pinctrl_usdhc3_200mhz: usdhc3grp200mhz {
++			fsl,pins = <
++				MX6QDL_PAD_SD3_CMD__SD3_CMD		0x170f9
++				MX6QDL_PAD_SD3_CLK__SD3_CLK		0x100f9
++				MX6QDL_PAD_SD3_DAT0__SD3_DATA0		0x170f9
++				MX6QDL_PAD_SD3_DAT1__SD3_DATA1		0x170f9
++				MX6QDL_PAD_SD3_DAT2__SD3_DATA2		0x170f9
++				MX6QDL_PAD_SD3_DAT3__SD3_DATA3		0x170f9
++				MX6QDL_PAD_SD3_DAT5__GPIO7_IO00		0x170f9 /* CD */
++				MX6QDL_PAD_NANDF_CS1__SD3_VSELECT	0x170f9
+ 			>;
+ 		};
+ 	};
+--- a/arch/arm/boot/dts/imx6qdl-gw54xx.dtsi
++++ b/arch/arm/boot/dts/imx6qdl-gw54xx.dtsi
+@@ -492,10 +492,13 @@
+ };
+ 
+ &usdhc3 {
+-	pinctrl-names = "default";
++	pinctrl-names = "default", "state_100mhz", "state_200mhz";
+ 	pinctrl-0 = <&pinctrl_usdhc3>;
++	pinctrl-1 = <&pinctrl_usdhc3_100mhz>;
++	pinctrl-2 = <&pinctrl_usdhc3_200mhz>;
+ 	cd-gpios = <&gpio7 0 GPIO_ACTIVE_HIGH>;
+ 	vmmc-supply = <&reg_3p3v>;
++	no-1-8-v; /* firmware will remove if board revision supports */
+ 	status = "okay";
+ };
+ 
+@@ -555,7 +558,6 @@
+ 				MX6QDL_PAD_NANDF_WP_B__NAND_WP_B	0xb0b1
+ 				MX6QDL_PAD_NANDF_RB0__NAND_READY_B	0xb000
+ 				MX6QDL_PAD_NANDF_CS0__NAND_CE0_B	0xb0b1
+-				MX6QDL_PAD_NANDF_CS1__NAND_CE1_B	0xb0b1
+ 				MX6QDL_PAD_SD4_CMD__NAND_RE_B		0xb0b1
+ 				MX6QDL_PAD_SD4_CLK__NAND_WE_B		0xb0b1
+ 				MX6QDL_PAD_NANDF_D0__NAND_DATA00	0xb0b1
+@@ -664,6 +666,34 @@
+ 				MX6QDL_PAD_SD3_DAT1__SD3_DATA1		0x17059
+ 				MX6QDL_PAD_SD3_DAT2__SD3_DATA2		0x17059
+ 				MX6QDL_PAD_SD3_DAT3__SD3_DATA3		0x17059
++				MX6QDL_PAD_SD3_DAT5__GPIO7_IO00		0x17059 /* CD */
++				MX6QDL_PAD_NANDF_CS1__SD3_VSELECT	0x17059
++			>;
++		};
++
++		pinctrl_usdhc3_100mhz: usdhc3grp100mhz {
++			fsl,pins = <
++				MX6QDL_PAD_SD3_CMD__SD3_CMD		0x170b9
++				MX6QDL_PAD_SD3_CLK__SD3_CLK		0x100b9
++				MX6QDL_PAD_SD3_DAT0__SD3_DATA0		0x170b9
++				MX6QDL_PAD_SD3_DAT1__SD3_DATA1		0x170b9
++				MX6QDL_PAD_SD3_DAT2__SD3_DATA2		0x170b9
++				MX6QDL_PAD_SD3_DAT3__SD3_DATA3		0x170b9
++				MX6QDL_PAD_SD3_DAT5__GPIO7_IO00		0x170b9 /* CD */
++				MX6QDL_PAD_NANDF_CS1__SD3_VSELECT	0x170b9
++			>;
++		};
++
++		pinctrl_usdhc3_200mhz: usdhc3grp200mhz {
++			fsl,pins = <
++				MX6QDL_PAD_SD3_CMD__SD3_CMD		0x170f9
++				MX6QDL_PAD_SD3_CLK__SD3_CLK		0x100f9
++				MX6QDL_PAD_SD3_DAT0__SD3_DATA0		0x170f9
++				MX6QDL_PAD_SD3_DAT1__SD3_DATA1		0x170f9
++				MX6QDL_PAD_SD3_DAT2__SD3_DATA2		0x170f9
++				MX6QDL_PAD_SD3_DAT3__SD3_DATA3		0x170f9
++				MX6QDL_PAD_SD3_DAT5__GPIO7_IO00		0x170f9 /* CD */
++				MX6QDL_PAD_NANDF_CS1__SD3_VSELECT	0x170f9
+ 			>;
+ 		};
+ 	};
+--- a/arch/arm/boot/dts/imx6qdl-gw551x.dtsi
++++ b/arch/arm/boot/dts/imx6qdl-gw551x.dtsi
+@@ -314,7 +314,6 @@
+ 				MX6QDL_PAD_NANDF_WP_B__NAND_WP_B	0xb0b1
+ 				MX6QDL_PAD_NANDF_RB0__NAND_READY_B	0xb000
+ 				MX6QDL_PAD_NANDF_CS0__NAND_CE0_B	0xb0b1
+-				MX6QDL_PAD_NANDF_CS1__NAND_CE1_B	0xb0b1
+ 				MX6QDL_PAD_SD4_CMD__NAND_RE_B		0xb0b1
+ 				MX6QDL_PAD_SD4_CLK__NAND_WE_B		0xb0b1
+ 				MX6QDL_PAD_NANDF_D0__NAND_DATA00	0xb0b1
+--- a/arch/arm/boot/dts/imx6qdl-gw552x.dtsi
++++ b/arch/arm/boot/dts/imx6qdl-gw552x.dtsi
+@@ -266,7 +266,6 @@
+ 				MX6QDL_PAD_NANDF_WP_B__NAND_WP_B	0xb0b1
+ 				MX6QDL_PAD_NANDF_RB0__NAND_READY_B	0xb000
+ 				MX6QDL_PAD_NANDF_CS0__NAND_CE0_B	0xb0b1
+-				MX6QDL_PAD_NANDF_CS1__NAND_CE1_B	0xb0b1
+ 				MX6QDL_PAD_SD4_CMD__NAND_RE_B		0xb0b1
+ 				MX6QDL_PAD_SD4_CLK__NAND_WE_B		0xb0b1
+ 				MX6QDL_PAD_NANDF_D0__NAND_DATA00	0xb0b1
diff --git a/target/linux/imx6/patches-4.1/040-ARM-dts-imx-ventana-add-pwm-nodes.patch b/target/linux/imx6/patches-4.1/040-ARM-dts-imx-ventana-add-pwm-nodes.patch
new file mode 100644
index 0000000..4de19b7
--- /dev/null
+++ b/target/linux/imx6/patches-4.1/040-ARM-dts-imx-ventana-add-pwm-nodes.patch
@@ -0,0 +1,264 @@
+--- a/arch/arm/boot/dts/imx6qdl-gw51xx.dtsi
++++ b/arch/arm/boot/dts/imx6qdl-gw51xx.dtsi
+@@ -231,6 +231,24 @@
+ 	status = "okay";
+ };
+ 
++&pwm2 {
++	pinctrl-names = "default";
++	pinctrl-0 = <&pinctrl_pwm2>; /* MX6_DIO1 */
++	status = "disabled";
++};
++
++&pwm3 {
++	pinctrl-names = "default";
++	pinctrl-0 = <&pinctrl_pwm3>; /* MX6_DIO2 */
++	status = "disabled";
++};
++
++&pwm4 {
++	pinctrl-names = "default";
++	pinctrl-0 = <&pinctrl_pwm4>; /* MX6_DIO3 */
++	status = "disabled";
++};
++
+ &uart1 {
+ 	pinctrl-names = "default";
+ 	pinctrl-0 = <&pinctrl_uart1>;
+@@ -352,6 +370,24 @@
+ 			>;
+ 		};
+ 
++		pinctrl_pwm2: pwm2grp {
++			fsl,pins = <
++				MX6QDL_PAD_SD1_DAT2__PWM2_OUT		0x1b0b1
++			>;
++		};
++
++		pinctrl_pwm3: pwm3grp {
++			fsl,pins = <
++				MX6QDL_PAD_SD4_DAT1__PWM3_OUT		0x1b0b1
++			>;
++		};
++
++		pinctrl_pwm4: pwm4grp {
++			fsl,pins = <
++				MX6QDL_PAD_SD4_DAT2__PWM4_OUT		0x1b0b1
++			>;
++		};
++
+ 		pinctrl_uart1: uart1grp {
+ 			fsl,pins = <
+ 				MX6QDL_PAD_SD3_DAT7__UART1_TX_DATA	0x1b0b1
+--- a/arch/arm/boot/dts/imx6qdl-gw52xx.dtsi
++++ b/arch/arm/boot/dts/imx6qdl-gw52xx.dtsi
+@@ -332,6 +332,18 @@
+ 	status = "okay";
+ };
+ 
++&pwm2 {
++	pinctrl-names = "default";
++	pinctrl-0 = <&pinctrl_pwm2>; /* MX6_DIO1 */
++	status = "disabled";
++};
++
++&pwm3 {
++	pinctrl-names = "default";
++	pinctrl-0 = <&pinctrl_pwm3>; /* MX6_DIO2 */
++	status = "disabled";
++};
++
+ &pwm4 {
+ 	pinctrl-names = "default";
+ 	pinctrl-0 = <&pinctrl_pwm4>;
+@@ -485,6 +497,18 @@
+ 			>;
+ 		};
+ 
++		pinctrl_pwm2: pwm2grp {
++			fsl,pins = <
++				MX6QDL_PAD_SD1_DAT2__PWM2_OUT		0x1b0b1
++			>;
++		};
++
++		pinctrl_pwm3: pwm3grp {
++			fsl,pins = <
++				MX6QDL_PAD_SD4_DAT1__PWM3_OUT		0x1b0b1
++			>;
++		};
++
+ 		pinctrl_pwm4: pwm4grp {
+ 			fsl,pins = <
+ 				MX6QDL_PAD_SD1_CMD__PWM4_OUT		0x1b0b1
+--- a/arch/arm/boot/dts/imx6qdl-gw53xx.dtsi
++++ b/arch/arm/boot/dts/imx6qdl-gw53xx.dtsi
+@@ -338,6 +338,18 @@
+ 	};
+ };
+ 
++&pwm2 {
++	pinctrl-names = "default";
++	pinctrl-0 = <&pinctrl_pwm2>; /* MX6_DIO1 */
++	status = "disabled";
++};
++
++&pwm3 {
++	pinctrl-names = "default";
++	pinctrl-0 = <&pinctrl_pwm3>; /* MX6_DIO2 */
++	status = "disabled";
++};
++
+ &pwm4 {
+ 	pinctrl-names = "default";
+ 	pinctrl-0 = <&pinctrl_pwm4>;
+@@ -492,6 +504,18 @@
+ 			>;
+ 		};
+ 
++		pinctrl_pwm2: pwm2grp {
++			fsl,pins = <
++				MX6QDL_PAD_SD1_DAT2__PWM2_OUT		0x1b0b1
++			>;
++		};
++
++		pinctrl_pwm3: pwm3grp {
++			fsl,pins = <
++				MX6QDL_PAD_SD4_DAT1__PWM3_OUT		0x1b0b1
++			>;
++		};
++
+ 		pinctrl_pwm4: pwm4grp {
+ 			fsl,pins = <
+ 				MX6QDL_PAD_SD1_CMD__PWM4_OUT		0x1b0b1
+--- a/arch/arm/boot/dts/imx6qdl-gw54xx.dtsi
++++ b/arch/arm/boot/dts/imx6qdl-gw54xx.dtsi
+@@ -427,6 +427,24 @@
+ 	};
+ };
+ 
++&pwm1 {
++	pinctrl-names = "default";
++	pinctrl-0 = <&pinctrl_pwm1>; /* MX6_DIO0 */
++	status = "disabled";
++};
++
++&pwm2 {
++	pinctrl-names = "default";
++	pinctrl-0 = <&pinctrl_pwm2>; /* MX6_DIO1 */
++	status = "disabled";
++};
++
++&pwm3 {
++	pinctrl-names = "default";
++	pinctrl-0 = <&pinctrl_pwm3>; /* MX6_DIO2 */
++	status = "disabled";
++};
++
+ &pwm4 {
+ 	pinctrl-names = "default";
+ 	pinctrl-0 = <&pinctrl_pwm4>;
+@@ -585,6 +603,24 @@
+ 			>;
+ 		};
+ 
++		pinctrl_pwm1: pwm1grp {
++			fsl,pins = <
++				MX6QDL_PAD_GPIO_9__PWM1_OUT		0x1b0b1
++			>;
++		};
++
++		pinctrl_pwm2: pwm2grp {
++			fsl,pins = <
++				MX6QDL_PAD_SD1_DAT2__PWM2_OUT		0x1b0b1
++			>;
++		};
++
++		pinctrl_pwm3: pwm3grp {
++			fsl,pins = <
++				MX6QDL_PAD_SD4_DAT1__PWM3_OUT		0x1b0b1
++			>;
++		};
++
+ 		pinctrl_pwm4: pwm4grp {
+ 			fsl,pins = <
+ 				MX6QDL_PAD_SD1_CMD__PWM4_OUT		0x1b0b1
+--- a/arch/arm/boot/dts/imx6qdl-gw551x.dtsi
++++ b/arch/arm/boot/dts/imx6qdl-gw551x.dtsi
+@@ -250,6 +250,18 @@
+ 	status = "okay";
+ };
+ 
++&pwm2 {
++	pinctrl-names = "default";
++	pinctrl-0 = <&pinctrl_pwm2>; /* MX6_DIO1 */
++	status = "disabled";
++};
++
++&pwm3 {
++	pinctrl-names = "default";
++	pinctrl-0 = <&pinctrl_pwm3>; /* MX6_DIO2 */
++	status = "disabled";
++};
++
+ &ssi1 {
+ 	status = "okay";
+ };
+@@ -343,6 +355,18 @@
+ 			>;
+ 		};
+ 
++		pinctrl_pwm2: pwm2grp {
++			fsl,pins = <
++				MX6QDL_PAD_SD1_DAT2__PWM2_OUT		0x1b0b1
++			>;
++		};
++
++		pinctrl_pwm3: pwm3grp {
++			fsl,pins = <
++				MX6QDL_PAD_SD1_DAT1__PWM3_OUT		0x1b0b1
++			>;
++		};
++
+ 		pinctrl_uart2: uart2grp {
+ 			fsl,pins = <
+ 				MX6QDL_PAD_SD4_DAT7__UART2_TX_DATA	0x1b0b1
+--- a/arch/arm/boot/dts/imx6qdl-gw552x.dtsi
++++ b/arch/arm/boot/dts/imx6qdl-gw552x.dtsi
+@@ -216,6 +216,18 @@
+ 	status = "okay";
+ };
+ 
++&pwm2 {
++	pinctrl-names = "default";
++	pinctrl-0 = <&pinctrl_pwm2>; /* MX6_DIO1 */
++	status = "disabled";
++};
++
++&pwm3 {
++	pinctrl-names = "default";
++	pinctrl-0 = <&pinctrl_pwm3>; /* MX6_DIO2 */
++	status = "disabled";
++};
++
+ &uart2 {
+ 	pinctrl-names = "default";
+ 	pinctrl-0 = <&pinctrl_uart2>;
+@@ -295,6 +307,18 @@
+ 			>;
+ 		};
+ 
++		pinctrl_pwm2: pwm2grp {
++			fsl,pins = <
++				MX6QDL_PAD_SD1_DAT2__PWM2_OUT		0x1b0b1
++			>;
++		};
++
++		pinctrl_pwm3: pwm3grp {
++			fsl,pins = <
++				MX6QDL_PAD_SD4_DAT1__PWM3_OUT		0x1b0b1
++			>;
++		};
++
+ 		pinctrl_uart2: uart2grp {
+ 			fsl,pins = <
+ 				MX6QDL_PAD_SD4_DAT7__UART2_TX_DATA	0x1b0b1
diff --git a/target/linux/imx6/patches-4.1/041-ARM-dts-imx-ventana-add-spi-support-for-gw52xx.patch b/target/linux/imx6/patches-4.1/041-ARM-dts-imx-ventana-add-spi-support-for-gw52xx.patch
new file mode 100644
index 0000000..29c995b
--- /dev/null
+++ b/target/linux/imx6/patches-4.1/041-ARM-dts-imx-ventana-add-spi-support-for-gw52xx.patch
@@ -0,0 +1,33 @@
+--- a/arch/arm/boot/dts/imx6qdl-gw52xx.dtsi
++++ b/arch/arm/boot/dts/imx6qdl-gw52xx.dtsi
+@@ -172,6 +172,14 @@
+ 	status = "okay";
+ };
+ 
++&ecspi3 {
++	fsl,spi-num-chipselects = <1>;
++	cs-gpios = <&gpio4 24 GPIO_ACTIVE_HIGH>;
++	pinctrl-names = "default";
++	pinctrl-0 = <&pinctrl_ecspi3>;
++	status = "okay";
++};
++
+ &fec {
+ 	pinctrl-names = "default";
+ 	pinctrl-0 = <&pinctrl_enet>;
+@@ -393,6 +401,15 @@
+ 			>;
+ 		};
+ 
++		pinctrl_ecspi3: escpi3grp {
++			fsl,pins = <
++				MX6QDL_PAD_DISP0_DAT0__ECSPI3_SCLK	0x100b1
++				MX6QDL_PAD_DISP0_DAT1__ECSPI3_MOSI	0x100b1
++				MX6QDL_PAD_DISP0_DAT2__ECSPI3_MISO	0x100b1
++				MX6QDL_PAD_DISP0_DAT3__GPIO4_IO24	0x100b1
++			>;
++		};
++
+ 		pinctrl_enet: enetgrp {
+ 			fsl,pins = <
+ 				MX6QDL_PAD_RGMII_RXC__RGMII_RXC		0x1b0b0
-- 
1.9.1
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