[OpenWrt-Devel] [PATCH V2] b53: override CPU port state on BCM5301X with CPU port other than 8

[Ian Kent]

On Sun, 2015-04-12 at 19:01 +0200, Rafał Miłecki wrote:
> Newer revisions (5+) of BCM53011 and probably all revs of BCM53012
> require overriding CPU port to work. So far we were handling it only for
> CPU port 8, but some devices may use e.g. port 5. In such case we need
> to use recently defined GMII_PORT registers.
> It was tested for regressions on BCM53011 revs 2 & 3. It was also
> confirmed to fix switch on some internal Broadcom board.

CPU port as 5 also allows the switch on my R8000 (BCM53012) rev 5 device
to function.

The puzzle is the the Vendor firmware uses port 8 as the cpu port (+ 5
and 7 for some unknown purpose) for these higher rev switches. We
clearly don't know what the relationship is between ports 5, 7 and 8 and
I suspect there's more to it than just configuring the three ports
properly. But my code to set ports 5, 7 and 8 when cpu is 8 might not be
correct either, don't know yet.

> 
> Signed-off-by: Rafał Miłecki <zajec5 at gmail.com>
> ---
> V2: Use new code branch to make (unused) port 8 branch reachable.
> ---
>  .../generic/files/drivers/net/phy/b53/b53_common.c      | 17 +++++++++++++++++
>  1 file changed, 17 insertions(+)
> 
> diff --git a/target/linux/generic/files/drivers/net/phy/b53/b53_common.c b/target/linux/generic/files/drivers/net/phy/b53/b53_common.c
> index d2bb51a..2079f80 100644
> --- a/target/linux/generic/files/drivers/net/phy/b53/b53_common.c
> +++ b/target/linux/generic/files/drivers/net/phy/b53/b53_common.c
> @@ -536,6 +536,23 @@ static int b53_switch_reset(struct b53_device *dev)
>  			   PORT_OVERRIDE_LINK);
>  	}
>  
> +	if (is5301x(dev)) {
> +		if (dev->sw_dev.cpu_port == 8) {
> +			/* TODO: Ports 5 & 7 require some extra handling */
> +		} else {
> +			u8 po_reg = B53_GMII_PORT_OVERRIDE_CTRL(dev->sw_dev.cpu_port);
> +			u8 gmii_po;
> +
> +			b53_read8(dev, B53_CTRL_PAGE, po_reg, &gmii_po);
> +			gmii_po |= GMII_PO_LINK |
> +				   GMII_PO_RX_FLOW |
> +				   GMII_PO_TX_FLOW |
> +				   GMII_PO_EN |
> +				   GMII_PO_SPEED_2000M;
> +			b53_write8(dev, B53_CTRL_PAGE, po_reg, gmii_po);
> +		}
> +	}
> +
>  	b53_enable_mib(dev);
>  
>  	return b53_flush_arl(dev);
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